operation is completed by making the
result characteristic 128 less than the
correct value, and a program inter­
ruption for exponent overflow takes
place. The result sign and fraction
remain correct, and, for AXR, the char­
acteristic of the low-order part remains
correct.
An exponent-underflow exception is
recognized when the characteristic of
the normalized sum would be less than
zero and the fraction is not zero. If
the exponent-underflow mask bit is one,
the operation is completed by making the
result characteristic 128 greater than
the correct value. The result sign and
fraction remain correct, and a program
interruption for exponent underflow
takes place. When exponent underflow
occurs and the exponent-underflow mask
bit is zero, a program interruption does
not take place; instead, the operation
is completed by making the result a true
zero. For AXR, no exponent underflow is
recognized when the characteristic of
the low-order part would be less than
zero but the characteristic of the
high-order part is zero or greater.
The result fraction is zero when the
intermediate-sum fraction, including the
guard di gi t, is zero. Wi th a zero
result fraction, the action depends on
the setting of the significance mask
bit. If the significance mask bit is
one, no normalization occurs, the inter­
mediate and final result characteristics
are the same, and a program interruption
for significance takes place. If the
significance mask bit is zero, the
program interruption does not occur;
instead, the result is made a true zero.
The R\ field for AER, AE, ADR, and AD,
and the R2 field for AER and ADR must
designate register 0, 2, 4, or 6. The R1 and R2 fields for AXR must designate
register 0 or 4. Otherwise, a specifi­
cation exception is recognized.
Resulting Condition Code: o
1
2
3
Result fraction zero
Result less than zero
Result greater than zero
Program Exceptions:
Access (fetch, operand 2 of AE and
AD only)
Exponent overflow
Exponent underflow
Operation (if the floating-point
facility is not installed, or,
for AXR, if the extended­
precision floating-point facil­
ity is not installed)
Significance
Specification
1. An example of the use of the ADD NORMALIZED instruction is given in
Appendix A.
2. Interchanging the two operands in a
floating-point addition does not
affect the value of the sum.
3. The ADD NORMALIZED instruction
normalizes the sum but not the
operands. Thus, if one or both
operands are unnormalized, preci­
sion may be lost during fraction
alignment.
ADD UNNORMALIZED AUR R \ , R:z [RR, Short Operands] , 3 E' I R\ I R2 0 8 12 15
AU Rt,D:z(X:z,B:z) [RX, Short Operands]
'7 E' I Rt I X 2 I B2 I O 2 0 8 12 16 20 31
AWR [RR, Long Operands]
o 8 12 15
AW [RX, Long Operands]
'6 E'
o 8 12 16 20 31
The second operand is added to the first
operand, and the unnormalized sum is
placed at the first-operand location.
The execution
identical to
except that:
of ADD
that of UNNORMALIZED is
ADD NORMALIZED, 1. When no carry is present after addition, the intermediate-sum
fraction is truncated to the proper
result-fraction length without a
left shift to eliminate leading
hexadecimal zeros and without the
corresponding reduction of the
characteristic.
2. Exponent underflow cannot occur. Chapter 9. Floating-Point Instructions 9-7

3. The guard digit does not partici­
pate in the recognition of a zero
result fraction. A zero result
fraction is recognized when the
fraction (that is, the inter­
mediate-sum fraction, excluding the
guard digit) is zero.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Resulting Condition Code: o Result fraction zero
1 Result less than zero
2 Result greater than zero
3
Program Exceptions:
Access (fetch, operand 2 of AU and
AW only)
Exponent overflow Operation (if the floating-point
facility is not installed)
Significance
Specification
Programming Notes 1. An example of the use of the ADD UNNORMALIZED instruction is given
in Appendix A.
2. Except when the result is made a
true zero, the characteristic of
the result of ADD UNNORMAlIZED is
equal to the greater of the two
operand characteristics, increased
by one if the fraction addition
produced a carry, or set to zero if
exponent overflow occurred. COMPARE CER R t , R2 [RR, Short Operands] '39' I R t I R:z 0 8 12 15 CE R
t ,D2(X2,B2
) [RX, Short Operands] , 79'
o 8 12 16 20 31 CDR [RR, Long Operands] o 8 12 15
9-8 System/370 Principles of Operation CD [RX, Long Operands] '69'
o 8 12 16 20 31
The first operand is compared with the
second operand, and the condition code
is set to indicate the result.
The comparison is algebraic and follows
the procedure for normalized floating­
point subtraction, except that the
difference is discarded after setting
the condition code and both operands
remain unchanged. When the difference,
including the guard digit, is zero, the
operands are equal. When a nonzero
difference is positive or negative, the
first operand is high or low, respec­
tively.
An exponent-overflow, exponent­
underflow, or significance exception
cannot occur.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a specification exception is recognized.
Resulting Condition Code: o
1
2
3 Operands equal
First operand low
First operand high
Program Exceptions:
Access (fetch, operand 2 of CE and CD only) Operation (if the floating-point
facility is not installed)
Specification
Programming Notes 1. Examples of the use of the COMPARE instruction are given in Appendix
A.
2. An exponent inequality alone is not
sufficient to determine the
inequality of two operands with the
same sign, because the fractions
may have different numbers of lead­
ing hexadecimal zeros.
3. Numbers with zero fractions compare equal even when they differ in sign
or characteristic.