DIVIDE DER [RR, Short Operands]
o 8 12 15
DE '70' o 8 12 16 20 31
DDR [RR, long Operands]
o 8 12 15 DO [RX, long Operands] '60' o 8 12 16 20 31
The first operand (the dividend) is
divided by the second operand (the divi­
sor), and the normalized quotient is
placed at the first-operand location. No remainder is preserved.
Floating-point division consists in
characteristic subtraction and fraction
division. The operands are first
normalized to eliminate leading hexade­
cimal zeros. The difference between the
dividend and divisor characteristics of
the normalized operands, plus 64, is
used as the characteristic of an inter­
mediate quotient.
All dividend and divisor fraction digits
participate in forming the fraction of
the intermediate quotient. The
intermediate-quotient fraction can have
no leading hexadecimal zeros, but a
right shift of one digit position may be
necessary with an increase of the char­
acteristic by one. The fraction is then
truncated to the proper result-fraction
length.
An exponent-overflow exception is recog­
nized when the characteristic of the
final quotient would exceed 127 and the
fraction is not zero. The operation is
completed by making the characteristic
128 less than the correct value. The
result is normalized, and the sign and
fraction remain correct. A program
interruption
occurs.
for exponent overflow
An exponent-underflow exception exists
when the characteristic of the final
quotient would be less than zero and the
fraction is not zero. If the exponent­
underflow mask bit is one, the operation
is completed by making the character­
istic 128 greater than the correct
value, and a program interruption for
exponent underflow occurs. The result
is normalized, and the sign and fraction
remain correct. If the exponent­
underflow mask bit is zero, a program
interruption does not take place;
instead, the operation is completed by
making the quotient a true zero.
Exponent underflow does not occur when
an operand characteristic becomes less
than zero during normalization of the
operands or when the intermediate­
quotient characteristic is less than
zero, as long as the final quotient can
be represented with the correct charac­
teristic.
When the divisor fraction is zero, a
floating-point-divide exception is
recognized. This includes the case of
division of zero by zero.
When the dividend fraction is zero, but
the divisor fraction is nonzero, the
quotient is made a true zero. No expo­
nent overflow or exponent underflow
occurs.
The sign of the quotient is determined
by the rules of algebra, except that the
sign is always plus when the quotient is
made a true zero.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Condition Code:
unchanged. Program Exceptions:
The code remains
Access (fetch, operand 2 of DD and
DE only)
Exponent overflow
Exponent underflow
Floating-point divide
Operation (if the floating-point
facility is not installed>
Specification Programming Note
Examples of the use of the DIVIDE instruction are given in Appendix A.
Chapter 9. Floating-Point Instructions 9-9
HALVE HER [RR, Short Operands]
o 8 12 15
HDR [RR, Long Operands]
o 8 12 15
The second operand is divided by 2, and
the normalized quotient is placed at the
first-operand location.
The fraction of the second operand is
shifted right one bit position, placing
the contents of the rightmost bit posi­
tion in the leftmost bit position of the
guard digit, and a zero is supplied to
the leftmost bit position of the frac­
tion. The intermediate result,
including the guard digit, is then
normalized, and the final result is
truncated to the proper length.
An exponent-underflow exception exists
when the characteristic of the final
result would be less than zero and the
fraction is not zero. If the exponent­
underflow mask bit is one, the operation
is completed by making the character­
istic 128 greater than the correct
value, and a program interruption for
exponent underflow occurs. The result
is normalized, and the sign and fraction
remain correct. If the exponent­
underflow mask bit is zero, a program
interruption does not take place;
instead, the operation is completed by
making the result a true zero.
When the fraction of the second operand
is zero, the result is made a true zero,
and no exponent underflow occurs.
The sign of the result is the same as
that of the second operand, except that
the sign is always plus when the
quotient is made a true zero.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized. Condition Code: unchanged.
Program Exceptions:
The
Exponent underflow
code remains
Operation (if the floating-point
facility is not installed)
Specification 9-10 System/370 Principles of Operation
Programming Notes
1. An example of the use of the HALVE instruction is given in Appendix A.
2. With short and long operands, the
halve operation is identical to a
divide operation with the number 2
as divisor. Similarly, the result
of HDR is identical to that of MD
or MDR with one-half as a multipli­
er. No multiply operation
corresponds to HER, since no multi­
ply operation produces short
results.
3. The result of HALVE is zero only
when the second-operand fraction is
zero, or when exponent underflow
occurs with the exponent-underflow
mask set to zero. A fraction with
zeros in every bit position, except
for a one in the rightmost bit
position, does not become zero
after the right shift. This is
because the one bit is preserved in
the guard-digit position and, when
the result is not made a true zero
because of exponent underflow,
becomes the leftmost bit after
normalization of the result. LOAD LER Ru R2 [RR, Short Operands]
'38' I R t I R2 0 8 12 15
LE Rt ,D2(X2,B2) [RX, Short Operands]
'78'
o 8 12 16 20 31
LDR [RR, Long Operands]
o 8 12 15
LD [RX, Long Operands]
o 8 12 16 20 31
The second operand is placed unchanged
at the first-operand location.
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