SXR [RR, Extended Operands]
'37' I Rt I R2 I o 8 12 15
The second operand is subtracted from
the first operand, and the normalized
difference is placed at the first­
operand location.
The execution of SUBTRACT NORMALIZED is
identical to that of ADD NORMALIZED, except that the second operand partic­
ipates in the operation with its sign
bit inverted.
The R t fi eld of SER, SE, SDR, and SD, and the R2 field of SER and SDR must
designate register 0, 2, 4, or 6. The
R t and R2 fields of SXR must designate
register 0 or 4. Otherwise, a specifi­
cation exception is recognized.
Resulting Condition Code:
o Result fraction zero
1 Result less than zero
2 Result greater than zero 3 Program Exceptions:
Access (fetch, operand 2 of SE and
SD only)
Exponent overflow
Exponent underflow
Operation (if the floating-point
facility is not installed, or,
for SXR, if the extended­
precision floating-point facil­
ity is not installed)
Significance
Specification
SUBTRACT UNNORMALIZED SUR [RR, Short Operands]
o 8 12 15
SU R
tl D
2
(X
2
,B
2
) [RX, Short Operands]
'7 F' I R t I X 2 I B2 I D2 0 8 12 16 20 31 SWR R t' R2 [RR, Long Operands]
'2F' I R t I R2 0 8 12 15 SW R
tl D
2
(X
2
,B
2
) [RX, Long Operands]
'6F' I R t I X2 I B2
o 8 12 16 20 31
The second operand is subtracted from
the first operand, and the unnormalized
difference is placed at the first­
operand location.
The execution of SUBTRACT UNNORMALIZED is identical to that of ADD UNNORMAlIZED, except that the second
operand participates in the operation
with its sign bit inverted.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Resulting Condition Code:
o Result fraction zero
1 Result less than zero 2 Result greater than zero 3 Program Exceptions:
Access (fetch, operand 2 of SU and
SW only)
Exponent overflow Operation (if the floating-point
facility is not installed)
Significance
Specification
Chapter 9. Floating-Point Instructions 9-15