currently connected channel set is imme­
diately disconnected from this CPU, regardless of whether the channel set
addressed by the instruction is opera­
tional or can be connected to this CPU. If the addressed channel set is current­
ly connected to this CPU, no channel-set
connection is changed, and condition
code 0 is set. If the addressed channel
set is operational and currently discon­
nected, it is connected to this CPU, and
condition code 0 is set.
When the addressed channel set is
connected to another CPU, it is not
connected to this CPU, and condition
code 1 is set.
When the addressed channel set is not
operational, no connection is performed,
and condition code 3 is set.
A serialization function is performed.
If a channel in the channel set which is
connected by means of this instruction
has an I/O interruption pending, and if
the CPU is enabled for I/O interruptions, the interruption is
recognized at the completion of this
instruction.
Resulting Condition Code: o
1
2
3 Connection completed Connection not performed; chan­
nel set connected to another CPU Not operational Program Exceptions: Operation (if the channel-set­
switching facility is not
installed) Privileged operation Programming Note The switching of channel sets and the
associated states of a channel set are
described in the section "Channel-Set Switching" in Chapter 4, "Control." DIAGNOSE '83'
o 8 31
The CPU performs built-in diagnostic
functions, or other model-dependent
functions. The purpose of the diagnos­
tic functions is to verify proper func­
tioning of equipment and to locate
faulty components. Other model-
dependent functions may include
disabling of failing buffers, reconfig­
uration of CPUs, storage, channel sets,
and channels, and modification of
control storage.
Bits 8-31 may be used as in the 51 or RS
formats, or in some other way, to speci­
fy the particular diagnostic function.
The use depends on the model.
The execution of the instruction may
affect the state of the CPU and the
contents of a register or storage
location, as well as the progress of an I/O operation. Some diagnostic func­
tions may cause the test indicator to be
turned on. Condition Code: The code is unpredict-
able. -- Program Exceptions: Privileged operation
Depending on the model, other
exceptions may be recognized. Programming Notes
1. Since the instruction is not
intended for problem-state-program
or control-program use, DIAGNOSE
has no mnemonic.
2. DIAGNOSE, unlike other
instructions, does not follow the
rule that programming errors are
distinguished from equipment
errors. Improper use of DIAGNOSE may result in false machine-check
indications or may cause actual
machine malfunctions to be ignored.
It may also alter other aspects of
system operation, including
instruction execution and channel­
program operation, to an extent
that the operation does not comply
with that specified in this publi­
cation. As a result of the
improper use of DIAGNOSE, the
system may be left in such a condi­
tion that the power-on reset or
initial-microprogram-loading (IML)
function must be performed. Since
the function performed by DIAGNOSE
may differ from model to model and
between versions of a model, the
program should avoid issuing DIAG­ NOSE unless the program recognizes
both the model number and version
code stored by STORE CPU 10. Chapter 10. Control Instructions 10-5

DISCONNECT CHANNEL SET
[S] 'B201' o 16 20 31
The addressed channel set is discon­
nected from the CPU to which it is
currently connected. If the channel set
is not connected, no operation is
performed.
The second-operand address, specified by
the B2 and D2 fields, is not used to
address data; bits 16-31 form the 16-bit
channel-set address. Bits 8-15 of the
second-operand address are ignored.
When the addressed channel set is opera­
tional but not connected to any CPU, no
disconnection operation is performed,
and condition code 0 is set.
When the addressed channel set is
connected either to the CPU issuing the DISCONNECT CHANNEL SET instruction or to
a CPU that is in the stopped or check­
stop state, the disconnection operation
is performed, and condition code 0 is
set.
When the addressed channel set is
connected to another CPU which is in the
operating state, which is being reset,
or for which a SIGNAL PROCESSOR reset order or IML order is pending, no
disconnection operation is performed, and condition code 1 is set.
When the addressed channel set is
connected to another CPU which is in the
operator-intervening state, it depends
on the model if condition code 0 or 1 is
set. The action taken in this case is
consistent with the condition code indi­
cated.
When the addressed channel set is not
operational, no disconnection operation
is performed, and condition code 3 is
set.
A serialization function is performed.
If a channel in a channel set which is
disconnected by this instruction has an I/O interruption pending, the inter­
ruption condition remains pending in the
channel while the channel set is in the
disconnected state.
Resulting Condition Code: o
1
2
3
Disconnection completed
Disconnection not performed;
channel set connected to anoth­
er CPU not in proper state
Not operational 10-6 System/370 Principles of Operation Program Exceptions:
Operation (if the channel-set­
switching facility is not
installed)
Privileged operation
Programming Note
The switching of channel sets and the
associated states of a channel set are
described in the section "Channel-Set
Switching" in Chapter 4, "Control."
EXTRACT PRIMARY ASN EPAR R t [RRE]
'B226'
o 16 24 28 31
The 16-bit PASN, bits 16-31 of control
register 4, is placed in bit positions
16-31 of general register R t • Bits 0-15 of the general register are set to
zeros.
Bits 16-23 and 28-31 of the instruction
are ignored.
Special Conditions
The instruction must be executed with OAT on; otherwise, a special-operation
exception is recognized. The special­
operation exception is recognized in
both the problem and supervisor states.
In the problem state, the extraction­
authority control, bit 4 of control
register 0, must be one; otherwise, a
privileged-operation exception is recog­
nized. In the supervisor state, the
extraction-authority-control bit is not
examined.
The priority of recognition of program
exceptions for the instruction is shown
in the figure "Priority of Execution:
EXTRACT PRIMARY ASN." Condition Code: unchanged. Program Exceptions:
The code
Operation (if the dual-address-
space facility is not
installed)
Privileged operation (extraction­
authority control is zero in
the problem state)
Special operation