Fetch op-1 doubleword PASN-d = PASN-old AND
Op-2-addr bit 29 = 0 Yes PSTD-old -~ PSTD-tmp LTD-old -~ LTD-tmp
AX-old -~ AX-tmp I 1 Yes I S -= No - I SASN-d = SASN-old
AND Op-2-addr bit 29 = 0 No AND ~------~ Op-2-addr bit 31 = 1 Yes -it No IASN available~I--------~)11 -~ Cond Codel I Yes -it Either old or new
space-switch-event-
control bit = 1
! No -it STD-p -~ PSTD-tmp lTD-p -~ LTD-tmp
AX-p -~ AX-tmp I '" Yes ~----~13 -~ Cond Codel No IASN availablel~--------~12 -~ Cond COdel I Yes -it PSTD-tmp-~ SSTD-tmp ISSTD-Old -~ SSTD-tmpl I -it '" IOP-2-addr 1\ No bit 30 = I I Yes -it -it IAX-d -~ Ax-newl AX-tmp -~ AX-new I ~ PSTD-tmp -~ PSTD-new ~ Op-2-addr bi t 31 = 0 I I Yes -it '" Yes IAuthorizedl No PKM-d -~ PKM-new LTD-tmp -~ LTD-new ~------~ SASN-d -~ SASN-new
SSTD-tmp ~ SSTD-new PASN-d -~ PASN-new Execution of LOAD ADDRESS SPACE PARAMETERS ~12 -~ Cond cOdel ~I 0 -~ Cond cOdel Chapter 10. Control Instructions 10-19

LOAD CONTROL o 8 12 16 20 31
The sat of control registers starting
with control register Rt and ending with
control register R3 is loaded from the
locations designated by the second­
operand address.
The storage area from which the contents
of the control registers are obtained
starts at the location designated by the
second-operand address and continues
through as many storage words as the
number of control registers specified.
The control registers are loaded in
ascending order of their register
numbers, starting with control register Rl and continuing up to and including
control register R
3
, with control regis­
ter 0 following control register 15.
The second operand remains unchanged.
Special Conditions The second operand must be designated on
a word boundary; otherwise, a specifica­
tion exception is recognized. Condition Code: unchanged.
Program Exceptions:
The code
Access (fetch, operand 2)
Privileged operation
Specification
Programming Notes
remains
1. To ensure that existing programs
operate correctly if and when new
facilities using additional
control-register positions are
defined, only zeros should be load­
ed in unassigned control-register
positions.
2. Loading of control registers on
some models may require a signif­
icant amount of time. This is
particularly true for changes in
significant parameters.
For example, the TLB may be cleared
of entries as a result of changing
the translation parameters in
control register 0 or as a result
of changing or enabling the
program-event-recording parameters
in control registers 9-11. Where 10-20 System/370 Principles of Operation
possible, the program should avoid
unnecessary loading of control
registers. In loading control
registers 9-11, most models attempt
to optimize for the case when the
bits of control register 9 are
zeros.
As another example, the translation
format, bits 8-12 of control regis­
ter 0, is initialized to all zeros
by initial CPU reset. An all-zero
value is an invalid translation
format, and, on some models,
results in purging the TLB even
though OAT may be off. Thus, the
program should avoid loading inval­
id values for this field. LOAD PSW
LPSW [S]
'82'
o 8 16 20 The current PSW is replaced
contents of the doubleword
location designated by the
operand address.
31
by the
at the
second-
Bits 8-15 of
ignored.
the instruction are
If the new PSW specifies the BC mode,
information in bit positions 16-33 of
the new PSW is not retained as the PSW
is loaded. When the PSW is subsequently
stored, these bit positions contain the
new interruption code and the
instruction-length code.
A serialization and checkpoint-synchron­
ization function is performed before or
after the operand is fetched and again
after the operation is completed.
Special Conditions The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized.
The value which is to be loaded by the
instruction is not checked for validity
before it is loaded. However, imme­
diately after loading, a specification
exception is recognized and a program
interruption occurs when any of the
following is true for the newly loaded PSW: • The EC mode is specified
12 is one) in a CPU that
have the translation
installed. (PSW bit
does not
facility