• Bit position 16 of an EC-mode PSW
is one, and DAS is not installed. • A one is introduced into an unas­
signed bit position of an EC-mode PSW (that is, any of bit positions 0, 2-4, 17, or 24-39).
In these cases, the operation is com­
pleted, and the resulting instruction­
length code is zero.
The test for a specification exception
after the PSW is loaded is described in
the section "Early Exception Recogni­
tion" in Chapter 6, Interruptions." It
may be considered as occurring early in
the process of preparing to execute the
subsequent instruction.
The operation is suppressed on all
addressing and protection exceptions. Condition Code: The code is set as
specified in the new PSW loaded. Program Exceptions:
Access (fetch, operand 2) Privileged operation
Specification LOAD REAL ADDRESS
LRA [RXJ
'B1'
o 8 12 16 20 31
The real address corresponding to the
second-operand virtual address is placed
in general register R t • The virtual address specified by the X 2 , B 2 , and D2 fields is translated by means
of the dynamic-address-translation
facility, regardless of whether the
current PSW specifies EC or BC mode, and
regardless of whether DAT is on or off.
When DAS is not installed, the trans­
lation is performed by using the current
contents of control registers 0 and 1.
When DAS is installed, the translation
is performed by using the current trans­
lation format in control register 0 and
the segment-table designation in either
control register 1 or 7. Control regis­
ter 1 is used if the current PSW specifies BC mode or specifies EC mode
with bit 16 set to zero. Control regis­
ter 7 is used if the current PSW specifies EC mode with bit 16 set to
one.
The translation is performed without the
use of the translation-lookaside buffer
(TLB). Sufficient zeros are appended on
the left of the resultant real address
to produce a 32-bit
then placed in general
translated address is
boundary alignment or
protection exceptions.
result, which is
register R t • The
not inspected for
for addressing or Condition code 0 is set when translation
can be completed, that is, when the
entry in each table lies within the
specified table length and its I bit is
zero. When the I bit in the segment-table
entry is one, condition code 1 is set,
and the real address of the segment­
table entry is placed in general regis­
ter R t • When the I bit in the page­
table entry is one, condition code 2 is
set, and the real address of the page­
table entry is placed in general
register R t • When either the segment­
table entry or the page-table entry;s
outside the table, condition code 3 is
set, and general register R t contains
the real address of the entry that would
have been fetched if the length
violation had not occurred. In all these cases, sufficient zeros are appended on the left of the resultant real address to produce a 32-bit result,
and the 32-bit result is placed in the
register.
Special Conditions A translation-specification exception is recognized when bits 8-12 of control
register 0 contain an invalid code, or
the segment-table entry or page-table
entry has the I bit with a value of zero
and has a format error.
The operation is suppressed on all
addressing exceptions.
Resulting Condition Code: o Translation available
1 Segment-table entry invalid (1
bit is one)
2 Page-table entry invalid (1 bit
is one) 3 Segment-or page-table length
exceeded Program Exceptions:
Addressing (segment-table entry or
page-table entry)
Operation (if the translation
facility is not installed) Privileged operation
Translation specification Programming Note Caution must be exercised in the use of LOAD REAL ADDRESS in a multiprocessing Chapter 10. Control Instructions 10-21

configuration. Since INVALIDATE PAGE TABLE ENTRY may set the I bit in storage
to one before causing the corresponding
entries in TLBs of other CPUs to be
cleared, the simultaneous execution of LOAD REAL ADDRESS on this CPU and INVAL­ IDATE PAGE TABLE ENTRY on another CPU may produce inconsistent results.
Because LOAD REAL ADDRESS accesses the
tables in storage, the page-table entry
may appear to be invalid (condition code
2) even though the corresponding TLB
entry has not yet been cleared, and the
TLB entry may remain in the TLB until
the completion of INVALIDATE PAGE TABLE ENTRY on the other CPU. There is no
guaranteed limit to the number of
instructions which may occur between the
completion of LOAD REAL ADDRESS and the
TLB being cleared of the entry. MOVE TO PRIMARY [SS] • DA • I R, I R, Is, I s, I o 8 12 16 20 32 36 47 MOVE TO SECONDARY MVCS DI (R I ,B I ),D:z(B
2
),R
3 [SS]
'DB' I RI I R3 I B I I I B2 I 0 8 12 16 20 32 36 47
The first operand is replaced by the
second operand. One operand is in the
primary address space, and the other is
in the secondary address space. The
accesses to the operand in the primary
space are performed by using the PSW key; the accesses to the operand in the
secondary space are performed by using
the key specified by the third operand.
The addresses of the first and second
operands are virtual, one operand
address being translated by means of the primary segment-table designation and
the other by means of the secondary
segment-table designation. Operand­ address translation is performed by
ignoring the state of the address­
space-control bit in the current PSW. For MOVE TO PRIMARY, movement is to the
primary space from the secondary space.
The first-operand address is translated
by using the primary segment table, and
the second-operand address is translated
by using the secondary segment table. 10-22 System/370 Principles of Operation For MOVE TO SECONDARY, movement is to
the secondary space from the primary
space. The first-operand address is
translated by using the secondary
segment table, and the second-operand
address is translated by using the
primary segment table.
Bit positions 24-27 of general register
R3 are used as the secondary-space
access key. Bit positions 0-23 and 28-31 of the register are ignored.
The contents of general register Rt are a 32-bit unsigned value called the true
length.
The contents of the general registers
just described are as follows:
True Length
o 31
R3 1////////////////////////IKey 1////1 o 24 28 31
The first and second operands are the
same length, called the effective
length. The effective length is equal
to the true length, or 256, whichever is
less. Access exceptions for the first and second operands are recognized only
for that portion of the operand within
the effective length. When the effec­
tive length is zero, no access
exceptions are recognized for the first
and second operands, and no movement
takes place.
Each storage operand is processed left
to right. The storage-operand­
consistency rules are the same as for MOVE (MVC), except that when the oper­
ands overlap in real storage, the use of
the common real-storage locations is not
necessarily recognized.
As part of the execution of the instruc­
tion, the value of the true length is
used to set the condition code. If the
true length is 256 or less, including
zero, the true length and effective
length are equal, and condition code 0 is set. If the true length is greater
than 256, the effective length is 256, and condition code 3 is set.
For both MOVE TO PRIMARY and MOVE TO SECONDARY, a serialization and check­
point-synchronization function is
performed before the operation begins and again after the operation is
completed.