Programming Hotes
1. MOVE WITH KEY can be used in a loop
to move a variable number of bytes
of any length, as follows: lOOP EHD
LA MVCK BC AR
AR
SR
B
RW,256
D1(R1,B1),D2(B2),R3
8,EHD B 1 ,RW B
2
,RW R 1 ,RW LOOP 2. The performance of MOVE WITH KEY on
most models may be significantly
slower than that of the MOVE (MVC) and MOVE LOHG instructions. There­
fore, MOVE WITH KEY should not be
used if the key of the source and
the target are the same. PROGRAM CAll PC [5]
'B218'
o 16 20 31
A two-level lookup is performed to
locate an entry-table entry (ETE). The
ETE contains an authorization-key mask;
an ASH; an entry parameter, which is
loaded into general register 4; and
information to update the PSW-key mask
in control register 3 and to replace the
problem-state bit and instruction
address in the PSW. The original
contents of the control-register and the
PSW fields are saved in general regis­
ters 3 and 14.
The ETE also causes a space-switching
operation to occur if it specifies a
nonzero ASH. When the ETE specifies a
zero ASH, the operation is called PROGRAM CALL to current primary (PC-cp); when the ETE specifies a nonzero ASH,
the operation is called PROGRAM CALL with space switching (PC-ss). When
space switching is specified, the new
PASH is loaded into control register 4
from the ETE and is used in a two-level
lookup to locate an ASH-second-table
entry (ASTE). From this ASTE, a new
PSTD, AX, and LTD are loaded into
control registers 1, 4, and 5, respec­
tively. Whether or not space switching
is specified, the previous PASH and PSTD are placed in the SASH and SSTD, respec­
tively, and the previous PASN is saved
in general register 3. PROGRAM CALL PC-Humber Translation
The second-operand address is not used
to address data; instead, the rightmost 20 bits of the address are used as a PC number and have the following format:
Second-Operand Address r------PC 1////////////1 LX EX
o 12 24 31
Linkage Index (LX): Bits 12-23 of the
second-operand address are the linkage
index and are used to select an entry
from the linkage table designated by the
linkage-table designation in control
register 5.
Entry Index (EX): Bits 24-31 of the
second-operand address are the entry
index and are used to select an entry
from the entry table designated by the
linkage-table entry.
Bits 0-11 of the second-operand address
are ignored.
The linkage-table and entry-table lookup
process is depicted in part 1 of the
figure "Execution of PROGRAM CALL." The
detailed definition for this table­
lookup process is in the section "PC-Humber Translation" in Chapter 5, "Program Execution." The entry-table
entry has the following format:
AKM ASH I 0-0 1 IA 1 P I 0 16 32 40 63
PARM EKM 1/////////1 64 96 112 127
LTE bits 1-7 and ETE bits 32-39 must be
zeros; otherwise, a PC-translation­ specification exception is recognized. After the entry-table entry has been
fetched, if the current PSW specifies
the problem state, the current PSW-key mask in control register 3 is tested
against the AKM field in the entry-table
entry to determine whether the program
is authorized to access this entry. The
AKM and PSW-key mask are AHDed, and if
the result is zero, a privileged­
operation exception is recognized. When PROGRAM CALL is executed in the supervi­
sor state, the AKM field is ignored.
If the result of the AHD of the AKM and
the PSW-key mask is not zero, or if the CPU is in the supervisor state, the
execution of the instruction continues. Chapter 10. Control Instructions 10-25

The PSW-key mask, bits 0-15 of control
register 3, is placed in bit positions 0-15 of general register 3, and the
current PASH, bits 16-31 of control
register 4, is placed in bit positions
16-31 of general register 3.
The current PSTD, bits 0-31 of control
register 1, is placed in control regis­
ter 7 to become the current SSTD.
The current PASH, bits 16-31 of control
register 4, is placed in bit positions
16-31 of control register 3 to become
the current SASH. Bits 40-62 of the current PSW (the
updated instruction address) are placed
in bit positions 8-30 of general regis­
ter 14. Bit 15 of the PSW (the
problem-state bit) is placed in bit
position 31 of general register 14.
Bits 0-7 of general register 14 are set
to zeros.
Bits 40-62 of the ETE, with a rightmost
zero appended, are placed in PSW bit
positions 40-63 (the instruction
address). Bit 63 of the ETE is placed
in PSW bit position 15 (the problem­
state bit).
Bits 64-95 of the ETE (the entry parame­
ter) are loaded into general register 4.
Bits 96-111 of the ETE (the EKM) are ORed with the PSW-key mask, bits 0-15 of
control register 3, and the result
replaces the PSW-key mask in control
register 3. PROGRAM CALL to Current Primary (PC-cp) If bits 16-31 of the ETE (the ASH) are
zeros, a PROGRAM CALL to current primary (PC-cp) is specified, and the operation
is completed after performing those
actions as described above.
The PC-cp operation is depicted in parts
1 and 2 of the figure "Execution of PROGRAM CALL." PROGRAM CALL with Space Switching (PC-ss) ----
If the ASH in the ETE is nonzero, a PROGRAM CAll with space switching (PC-ss) instruction is specified, and
the ASH is translated by means of a
two-level table lookup.
The PC-ss operation is depicted in parts
1, 2 and 3 of the figure "Execution of PROGRAM CAll." The PC-ss operation is
completed as follows: 10-26 System/370 Principles of Operation Bits 16-25 of the ETE are used as a 10-bit AFX to index into the ASH first
table, and bits 26-31 are used as a six-bit ASX to index into the ASH second
table specified by the AFX. The ASH table-lookup process is described in the
section "ASH Translation" in Chapter 3,
"Storage." The exceptions associated
with ASH translation are collectively
called ASH-translation exceptions.
These exceptions and their priority are
described in Chapter 6, "Interruptions."
Bits 16-31 of the entry-table entry are
placed in bit positions 16-31 of control
register 4 as the new PASH. Bits 64-95 of the ASH-second-table entry
(the STD) are loaded into control regis­
ter 1 as the new PSTD.
Bits 32-47 of the ASH-second-table entry
(the AX) are loaded into bit positions 0-15 of control register 4 as the new
authorization index.
Bits 96-127 of the ASH-second-table
entry (the LTD) are loaded into control
register 5 as the new linkage-table
designation.
For both the PC-cp and PC-ss operations,
a serialization and checkpoint-synch­
ronization function is performed before
the operation begins and again after the
operation is completed.
Special Conditions The instruction can be executed only
when the CPU is in primary-space mode
and the subsystem-linkage control, bit 0 of control register 5, is one. If the CPU is in real mode or secondary-space
mode, or if the subsystem-linkage
control is zero, a special-operation
exception is recognized. In addition,
the PC-ss instruction can be executed
only when the ASH-translation control, bit 12 of control register 14, is one.
If PC-ss is attempted with the ASH­ translation control zero, a special­
operation exception is recognized. The
special-operation exception is recog­
nized in both the problem and supervisor
states.
When, for PC-ss, the space-switch­
event-control bit, bit 31 of control
register 1, is one either before or
after the execution of the instruction,
a space-switch-event program inter­
ruption occurs after the operation is completed. A space-switch-event program
interruption also occurs after the
completion of a PC-ss operation if a PER event is reported.
The operation is suppressed on all
addressing exceptions.