Special Conditions Since the secondary space is accessed,
the operation is performed only when the secondary-space control, bit 5 of
control register 0, is one and OAT is
on. When either the secondary-space
control is zero or OAT is off, a
special-operation exception is recog­
nized. The special-operation exception
is recognized in both the problem and
supervisor states.
In the problem state, the operation is
performed only if the secondary-space
access key is valid, that is, if the
corresponding PSW-key-mask bit in
control register 3 is one. Otherwise, a
privileged-operation exception is recog­
nized. In the supervisor state, any
value for the secondary-space access key
is valid.
The priority of the recognition of
exceptions and condition codes is shown
1n the figure "Priority of Execution: MOVE TO PRIMARY and MOVE TO SECONDARY." Resulting Condition Code: o True length less than or equal
to 256
1
2
3 True length greater than 256
Program Exceptions:
Access (fetch, primary virtual ad­
dress, operand 2, MVCS; fetch,
secondary virtual address, op­
erand 2, MVCPi store, secondary
virtual address, operand 1, MVCSj store, primary virtual
address, operand 1, MVCP) Operation (if the dual-address-
space facility is not
installed)
Privileged operation (selected
PSW-key-mask bit is zero in the problem state)
Special operation
1.-6. Exceptions with the same pri­
ority as the priority of pro­
gram-interruption conditions
for the general case.
7.A Access exceptions for second
and third instruction half­
words.
7.B.1 Operation exception if the dual-address-space facility is
not installed.
7.B.2 Special-operation exception due
to the secondary-space control,
bit 5 of control register 0, being zero or to OAT being off.
8. Privileged-operation exception
due to selected PSW-key-mask
bit being zero in the problem
state.
9. 10. Completion due to length zero.
Access exceptions for operands.
Priority of Execution: MOVE TO PRIMARY and MOVE TO SECONDARY Programming Notes
1. MOVE TO PRIMARY and MOVE TO SECOND­ ARY can be used in a loop to move a
variable number of bytes of any
length. See the programming note
under MOVE WITH KEY. 2. MOVE TO PRIMARY and MOVE TO SECOND­ ARY should be used only when move­
ment is between different address
spaces. The performance of these
instructions on most models may be
significantly slower than MOVE WITH KEY, MOVE (MVC), or MOVE LONG. In
addition, the definition of over­
lapping operands for MOVE TO PRIMARY and MOVE TO SECONDARY is
not compatible with the more
precise definitions for MOVE (MVC), MOVE WITH KEY, or MOVE LONG. Chapter 10. Control Instructions 10-23

MOVE WITH KEY MVCK [55] 'D9' I R, I R, I 8, I 8, o 8 12 16 20 32 36 47
The first operand is replaced by the
second operand. The fetch accesses to
the second-operand location are
performed by using the key specified in
the third operand, and the store
accesses to the first-operand location
are performed by using the PSW key. Bit positions 24-27 of general register
R3 are used as the source access key.
Bit positions 0-23 and 28-31 of the
register are ignored.
The contents of general register R, are
a 32-bit unsigned value called the true
length.
The contents of the general registers
just described are as follows:
True Length
o 31
R3 1////////////////////////IKey 1////1 o 24 28 31
The first and second operands are the
same length, called the effective
length. The effective length is equal
to the true length, or 256, whichever is
less. Access exceptions for the first
and second operands are recognized only
for that portion of the operand within
the effective length. When the effec­
tive length is zero, no access
exceptions are recognized for the first
and second operands, and no movement
takes place.
Each storage operand is processed left
to right. When the storage operands
overlap, the result is obtained as if
the operands were processed one byte at
a time and each result byte were stored
immediately after the necessary operand
byte was fetched. The storage-operand­
consistency rules are the same as for
the MOVE (MVC) instruction.
As part of the execution of the instruc­
tion, the value of the true length is
used to set the condition code. If the
true length is 256 or less, including zero, the true length and effective 10-24 5ystem/370 Principles of Operation length are equal, and condition code 0 is set. If the true length is greater
than 256, the effective length is 256,
and condition code 3 is set.
Special Conditions In the problem state, the operation is
performed only if the source access key
is valid, that is, if the corresponding P5W-key-mask bit in control register 3
is one. Otherwise, a privileged­
operation exception is recognized. In
the supervisor state, any value for the
source access key is valid.
The priority of the recognition of
exceptions and condition codes is shown
in the figure "Priority of Execution: MOVE WITH KEY Instruction."
o
1
2
3
True length less than or equal
to 256
True length greater than 256 Program Exceptions:
Access (fetch, operand 2; store,
operand 1) Privileged operation (selected PSW-key-mask bit is zero in the
problem state) Operation (if the dual-address-
space facility is not
installed)
1.-6. Exceptions with the same pri­
ority as the priority of pro­
gram-interruption conditions
for the general case.
7.A Access exceptions for second
and third instruction half­
words.
7.B
8. Operation exception if the
dual-address-space facility is
not installed. Privileged-operation exception
due to selected PSW-key-mask bit being zero in the problem
state.
9. Completion due to length zero. 10. Access exceptions for operands. Priority of Execution: MOVE WITH KEY