CR14 (x4) (x16) PKM ASN I oJ, ASH First Table L I---T---T---r-- R
I AS TO (xl6)
o CR4 before
(xl/4) ASH Second Table R oJ, R
I ATO STO (x4)
Authority Table r----------
e I P S oJ, CRl afterl PSTO oJ, CR7 afterl SSTO exception if P bit is zero or if table length is exceeded
R: Address is real
lTl I CR4 __ A_X __ __ CR5 after I l TO Execution of PROGRAM TRANSFER (Part 2 of 2): PT-ss Chapter 10. Control Instructions 10-35

PURGE TLB
PTLB [S] 'B20D' 1////////////////1 o 16 31
The translation-lookaside buffer (TLB)
of this CPU is cleared of entries. No
change is made to the contents of
addressable storage or registers.
Bits 16-31
ignored.
of the instruction are
The TLB appears cleared of its original
contents beginning with the fetching of
the next sequential instruction. The
operation is not signaled to any other CPU. A serialization function is performed. Condition Code: The
unchanged.
Program Exceptions:
code remains Operation (if the translation
facility is not installed)
Privileged operation
READ DIRECT RDD [SI]
'85'
o 8 16 20 31
The contents of the 12 field are made available as signal-out timing signals.
A direct-in data byte is accepted from
an external device in the absence of a
hold signal and is placed at the
location designated by the first-operand
address.
When the INVALIDATE PAGE TABLE ENTRY instruction is not installed, the
first-operand address is a logical
address, and is subject to the normal
access exceptions and to the PER
storage-alteration event.
When the INVALIDATE PAGE TABLE ENTRY instruction is installed, the first­
operand address is a real address and is
not subject to dynamic address trans­
lation. Addressing, key-control led­
protection, and low-address-protection
exceptions apply. The PER storage­
alteration event does not apply.
The contents of the 12 field are made
available on a set of eight signal-out 10-36 System/370 Principles of Operation
lines as O.S-microsecond to
1.0-microsecond timing signals. These
signal-out lines are also used in the
WRITE DIRECT instruction. On a ninth
line (read out), a O.S-microsecond to
1.O-microsecond timing signal is made
available coincident with these timing The read-out line is distinct
from the write-out line in the WRITE DIRECT instruction. No checking bits
are made available with the eight
instruction bits.
Eight data bits are accepted from a set
of eight direct-in lines when the hold
signal on the hold-in line is absent.
The hold signal is sampled after the
read-out signal has been completed and
should be absent for at least 0.5 micro­
second. No checking bits are accepted
with data signals, but a checking-block
code is generated as the data is placed
in storage. When the hold signal is not
removed, the CPU does not complete the
instruction.
A serialization function is performed
before the signals are made available
and again after the first-operand byte
is placed in storage.
An excessively long instruction
execution may result in omission of
updating of the interval timer. Condition Code:
unchanged.
The code remains
Program Exceptions:
Access (store, operand 1; access
applies only if the INVALIDATE
PAGE TABLE ENTRY instruction is
not installed)
Addressing (operand 1) Operation (if the direct-control
facility is not installed)
Privileged operation
Protection (store, operand 1; key­
controlled protection and low­
address protection)
RESET REFERENCE BIT
RRB [S]
'B213'
o 16 20 31
The reference bit in the storage key for
the 2K-byte block that is designated by
the second-operand address is set to
zero.
Bits 8-20 of the second-operand address
designate a 2K-byte block in real stor­
age. Bits 0-7 and 21-31 of the address
are ignored.