When the storage-key 4K-byte-block
facility is not installed, all blocks
are double-key 4K-byte blocks, and the
operation proceeds normally.
When the storage-key 4K-byte-block
facility is installed, all blocks are
single-key 4K-byte blocks, and the
action depends on the setting of the
storage-key-exception-control bit, bit 7
of control register O. If the bit is a special-operation exception is
recognized. If the bit is one, the
operation is performed on the single key
for the 4K-byte block.
Because it is a real address, the
address designating the storage block is
not subject to dynamic address trans­
lation. The reference to the storage
key is not subject to a protection
exception.
The values of the remalnlng bits of the
storage key, including the change bit,
are not affected.
The condition code is set to reflect the
state of the reference and change bits
before the reference bit is set to zero.
Special Conditions When the storage-key 4K-byte-block
facility is installed and the storage­
key exception-control bit (bit 7 of
control register 0) is zero, a special­
operation exception is recognized.
Resulting Condition Code: 0 Reference bit zero; change bit
zero
1 Reference bit zero; change bit
one
2 Reference bit one; change bit
zero
3 Reference bit one; change bit
one
Program Exceptions:
Addressing (operand 2)
Operation (if the translation
facility is not installed)
Privileged operation
Special operation
RESET REFERENCE BIT EXTENDED
RRBE [RRE]
'B22A'
o 16 24 28 31
The reference bits in the storage keys
for the 4K-byte block that is addressed
by the contents of general register R2
are set to zeros. The contents of
general register R t are ignored.
Bits 16-23
ignored.
of the instruction are
The contents of general register R2 are
treated as a 31-bit real address of a
4K-byte block in storage. Bits 1-19 of
the register designate the 4K-byte
block, and bits 0 and 20-31 of the
register are ignored.
When the storage-key 4K-byte-block
facility is not all blocks
are double-key 4K-byte blocks. The key
for the first 2K-byte block within the
4K-byte block designated by the instruc­
tion is called the low-order key. The
key for the second 2K-byte block is
called the high-order key. The refer­
ence bits of both the low-order and
high-order keys are set to zeros.
When the storage-key 4K-byte-block
facility is installed, all blocks are
single-key 4K-byte blocks. The refer­
ence bit in the single key is set to
zero.
Because it is a real address, the
address designating the storage block is
not subject to dynamic address trans­
lation. The reference to the storage
key is not subject to a protection
exception.
The remaining
including the
affected.
bits of the storage key,
change bit, are not
The condition code is set to reflect the
state of the reference and change bits
before the reference bit is set to zero.
If the addressed block is a single-key
4K-byte block, the reference and change
bits in the single key are used. If the
block is a double-key 4K-byte block, the
condition code is set as a function of
the OR of the change bits from the low­
order and high-order keys and as a
function of the OR of the reference bits
from the low-order and high-order keys.
Resulting Condition Code: 0 Reference bit zero; change bit
zero
1 Reference bit zero; change bit
one
2 Reference bit one; change bit
zero
3 Reference bit one; change bit
one
Program Exceptions:
Addressing (address specified by
general register R
2
) Chapter 10. Control Instructions 10-37

Operation Cif the storage-key­
instruction-extension facility
is not installed)
Privileged operation
SET ADDRESS SPACE CONTROL SAC [S]
'B219'
o 16 20 31
Bits 20-23 of the second-operand address
are used as a code to set the address­
space-control bit in the PSW. The
second-operand address is not used to
address data; instead, bits 20-23 form
the code. Bits 8-19 and 24-31 of the
second-operand address are ignored.
Bits 20-22 of the second-operand address
must be zeros; otherwise, a specifica­
tion exception is recognized.
The following figure summarizes the
operation of SET ADDRESS SPACE CONTROL: Second-Operand Address I////////////////////Icodel////////I o 20 24 31 0000 0001 All others
Primary space
Secondary space
Invalid
Result in PSW Bit II o
1 Unchanged A serialization and checkpoint-synchron­
ization function is performed before the
operation begins and again after the
operation is completed.
Special Conditions
The operation is performed only when the
secondary-space control, bit 5 of
control register 0, is one and DAT is
on. When either the secondary-space
control is zero or DAT is off, a
special-operation exception is recog­
nized. The special-operation exception
is recognized in both the problem and
supervisor states.
The priority of recognition of program
exceptions for the instruction is shown 10-38 System/370 Principles of Operation in the figure "Priority of
SET ADDRESS SPACE CONTROL." Execution:
Condition Code: unchanged. The code remains
Program Exceptions:
Operation Cif the dual-address-
space facility is not
installed)
Special operation
Specification
1.-6. Exceptions with the same pri­
ority as the priority of pro­
gram-interruption conditions
for the general case.
7.A Access exceptions for second
instruction halfword.
7.B.1 Operation exception if the
dual-address-space facility
is not installed.
7.B.2 Special-operation exception
due to DAT being off or the
secondary-space control,
8.
bit 5 of control register 0, being zero.
Specification exception due to
nonzero value in bits 20-22 of
the second-operand address.
Priority of Execution: SET ADDRESS SPACE CONTROL Programming Notes
1. SET ADDRESS SPACE CONTROL is
defined in such a way that the mode
to be set can be placed directly in
the displacement field of the
instruction or can be specified
from the same bit positions of a
general register as saved by INSERT
ADDRESS SPACE CONTROL. 2. Predictable program operation is
ensured in secondary mode only when
the instructions are fetched from
virtual-address locations which
translate to the same real address
by means of both the primary and
secondary segment tables. Thus, a
program should not enter
secondary-space mode if it is not
aware of the virtual-to-real
mapping in both the primary and
secondary spaces.