SET STORAGE KEY SSK [RR] '08' o 8 12 15
The storage key for the 2K-byte block
that is addressed by the contents of
general register R2 is replaced by bits
from general register R t • Bits 8-20 of general register R2 desig­
nate a 2K-byte block in real storage.
Bits 0-7 and 21-27 of the register are
ignored. Bits 28-31 of the register
must be zeros; otherwise, a specifica­
tion exception is recognized. When the storage-key 4K-byte-block
facility is not installed, all blocks are double-key 4K-byte blocks, and the operation proceeds normally. When the storage-key 4K-byte-block
facility is installed, all blocks are
single-key 4K-byte blocks, and the oper­
ation depends on the setting of the
storage-key-exception-control bit, bit 7
of control register o. If the bit is zero, a special-operation exception is recognized. If the bit ;s one, the
operation is performed on the single key for the 4K-byte block. Because it is a real address, the
address designating the storage block is not subject to dynamic address trans­
lation. The reference to the storage
key is not subject to a protection
exception.
The new seven-bit storage-key value is
obtained from bit positions 24-30 of
general register R t • The contents of
bit positions 0-23 and 31 of the regis­
ter are ignored. When the translation
facility is not installed, bits 29 and 30 are ignored.
A serialization and checkpoint­
synchronization function is performed
before the operation begins and again
after the operation is completed. Special Conditions Bits 28-31 of general register R2 must be zeros; otherwise, a specification
exception is recognized.
When the storage-key 4K-byte-block
facility is installed and the storage­
key-exception-control bit (bit 7 of
control register 0) is zero, a special­
operation exception is recognized. Condition unchanged.
Program Exceptions:
The
Addressing (address
general register
Privileged operation Special operation
Specification SET STORAGE KEY EXTENDED
code
[RRE]
'B22B'
o 16 24 remains by
28 31
The storage keys for the 4K-byte block
that is addressed by the contents of
general register R2 are replaced by bits
from general register R t • Bits 16-23
ignored.
of the instruction are
The contents of general register R2 are
treated as a 31-bit real address ofa
4K-byte block in storage. Bits 1-19 of
the register designate the 4K-byte
block, and bits 0 and 20-31 of the
register are ignored. When the storage-key 4K-byte-block
facility is not installed, all blocks are double-key 4K-byte blocks. The key
for the first 2K-byte block within the
4K-byte block designated by the instruc­
tion is called the low-order key. The key for the second 2K-byte block is
called the high-order key. Both the
low-order key and the high-order key are
replaced. The two keys are not neces­ sarily updated concurrently.
When the storage-key 4K-byte-block
facility is installed, all blocks are
single-key 4K-byte blocks, and the single key is replaced.
Because it is a real address, the
address designating the storage block is
not subject to dynamic address trans­
lation. The reference to the storage
key is not subject to a protection
exception.
The new seven-bit storage-key value is
obtained from bit positions 24-30 of
general register R t • The contents of
bit positions 0-23 and 31 of the regis­
ter are ignored.
A serialization and checkpoint­
synchronization function is performed before the operation begins and again
after the operation is completed. Chapter 10. Control Instructions 10-45

Condition Code: unchanged.
Program Exceptions:
The code remains
Addressing (address specified by
general register R
2
) Operation (if the storage-key­
instruction-extension facility
is not installed)
Privileged operation
SET SYSTEM MASK
[S] '80' o 8 16 20 31
Bits 0-7 of the current PSW are replaced
by the byte at the location designated
by the second-operand address.
Bits 8-15 of
ignored.
Special Conditions the instruction are When the translation facility is
installed, the execution of the instruc­ tion is subject to the SSM-suppression­
control bit, bit 1 of control register
o. When the bit is zero, the instruc­
tion is executed normally. When the bit is one and the CPU is in the supervisor
state, a special-operation exception is
recognized.
The value to be loaded into the PSW is not checked for validity before loading.
However, immediately after loading, a
specification exception is recognized,
and a program interruption occurs, if the CPU is in EC mode and the contents
of bit positions 0 and 2-4 of the PSW are not all zeros. In this case, the
instruction is completed, and the
instruction-length code is set to 2.
The specification exception, which is
listed as a program exception for this
instruction, is described in the section
"Early Exception Recognition" in Chapter
6, Interruptions." This exception may
be considered as caused by execution of
this instruction or as occurring early
in the process of preparing to execute
the subsequent instruction.
The operation is suppressed on all
addressing and protection exceptions. Condition Code: unchanged.
The code remains 10-46 System/370 Principles of Operation
Program Exceptions:
Access (fetch, operand 2)
Privileged operation
Special operation
Specification
Programming Note
SET SYSTEM MASK is frequently used in
the BC mode to disable or enable the CPU for I/O or external interruptions.
Hence, suppressing the execution of SET SYSTEM MASK by means of the SSM­
suppression-control bit, bit 1 of
control register 0, may be useful when
converting a program written for a
BC-mode PSW to operate with an EC-mode PSW. SIGNAL PROCESSOR SIGP [RS]
'AE'
o 8 12 16 20 31
An eight-bit order code is transmitted
to the CPU designated by the CPU address
contained in the third operand. The
result is indicated by the condition
code and may be detailed by status
assembled in the first-operand location.
The second-operand address is not used
to address data; instead, bits 24-31 of
the address contain the eight-bit order
code. Bits 8-23 of the second-operand
address are ignored. The order code
specifies the function to be performed
by the addressed CPU. The assignment
and definition of order codes appear in
the section "CPU Signaling and Response"
in Chapter 4, "Control."
The 16-bit binary number contained in
bit positions 16-31 of general R3 forms the CPU address. Bits 0-15 of
the register are ignored.
The operands just described have the
following formats:
General register designated by Rt:
Status
o 31