General register designated by R3: 1////////////////1 CPU Address
o 16 31
Second-operand address:
////////////////////////
o 24 31
A serialization function is performed
before the operation begins and again
after the operation is completed.
When the order code is accepted and no
nonzero status is returned, condition
code 0 is set. When status information
is generated by this CPU or returned by
the addressed CPU, the status is placed
in general register Rt, and condition
code 1 is set.
When the access path to the addressed CPU is busy, or the addressed CPU is operational but in a state where it cannot respond to the order code, condi­
tion code 2 is set.
When the addressed CPU is not opera­
tional (that is, it is not provided in
the i nstallati on, it is not in the
configuration, it is in any of certain
customer-engineer test modes, or its
power is off), condition code 3 is set.
Resulting Condition Code: o Order code accepted
1 Status stored
2 Busy
3 Not operational
Program Exceptions:
Operation (if the multiprocessing
facility is not installed)
Privileged operation
Programming Notes
1. A more detailed discussion of the
condition-code settings for SIGNAL PROCESSOR is contained in the
section "CPU Signaling and
Response" in Chapter 4, "Control."
2. To ensure that presently written
programs wi!! be executed properly
when new faci!ities using addi­
tional bits are installed, only
zeros should appear in the unused
bit positions of the second-operand
address and in bit positions 0-15 of general register R
3
• 3. Certain SIGNAL PROCESSOR orders are
provided with the expectation that
they will be used primarily in
special circumstances. Such orders
may be implemented with the aid of an auxiliary maintenance or service
processor, and, thus, the execution
time may take several seconds.
Unless all of the functions
provided by the order are required,
combinations of other orders, in
conjunction with appropriate
programming support, can be
expected to provide a specific
function more rapidly. The
emergency-signal, external-call,
and sense orders are the only
orders which are intended for
frequent use. The following orders
are intended for infrequent use,
and performance therefore may be
much slower than for frequently
used orders: IML, restart, start,
stop, stop and store status, and
all the reset orders. STORE CLOCK COMPARATOR [S] '8207' o 16 20 31
The current value of the clock compara­
tor is stored at the doubleword location
designated by the second-operand
address. Zeros are provided for the rightmost bit
positions of the clock comparator that
are not compared with the TOO clock.
Special Conditions The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized. Condition Code: The code remains
unchanged.
Program Exceptions:
Access (store, operand 2)
Operation (if the CPU-timer and
clock-comparator facility is
not installed)
Privileged operation
Specification Chapter 10. Control Instructions 10-47

STORE CONTROL [RS]
'B6'
o 8 12 16 20 31
The set of control registers starting
with control register Rt and ending with
control register R3 is stored at the
locations designated by the second­
operand address.
The storage area where the contents of
the control registers are placed starts
at the location designated by the
second-operand address and continues
through as many storage words as the
number of control registers specified.
The contents of the control registers
are stored in ascending order of their
register numbers, starting with control register R, and continuing up to and
including control register R3, with
control register 0 following control
register 15. The contents of the
control registers remain unchanged.
The information stored for unassigned
control-register positions, or positions
associated with a facility which is not
installed, is unpredictable.
Special Conditions
The second operand must be designated on
a word boundary; otherwise, a specifica­
tion exception is recognized.
Condition Code:
unchanged. Program Exceptions:
The code
Access (store, operand 2) Privileged operation
Specification Programming Note
remains
Although STORE CONTROL may provide zeros
in the bit positions corresponding to
the unassigned register positions, the
program should not depend on such zeros. 10-48 System/370 Principles of Operation STORE CPU ADDRESS STAP [S]
'B212'
o 16 20 31
The CPU address by which this CPU is
identified in a multiprocessing config­
uration is stored at the halfword
location designated by the second­
operand address.
The operand must be designated on a
halfword boundary; otherwise, a specifi­
cation exception is recognized.
Condition Code:
unchanged.
Program Exceptions:
The code
Access (store, operand 2)
remains Operation (if the multiprocessing
facility is not installed) Privileged operation
Specification STORE CPU 10 [S] 'B202' o 16 20 31
Information identifying the CPU is
stored at the doubleword location desig­
nated by the second-operand address.
The information stored has the following
format:
o
32
8
Model
Number
CPU Identification
Number
48
Maximum MCEL
Length
31
63
Bit positions 0-7 contain the version
code. The format and significance of
the version code depend on the model.
Bit positions 8-31 contain the CPU iden­
tification number, consisting of six
four-bit digits. Some or all of these