digits are selected from the physical
serial number stamped on the CPU. The
contents of the CPU-identification­ number field, in conjunction with the
model number, permit unique identifica­ tion of the CPU. Bit positions 32-47 contain the model
number, consisting of four digits:
leftmost zero digits, if necessary,
followed by the digits of the System/370 model number. For example, a Model 145
or 3033 system would store 0145 hex or 3033 hex, respectively.
Bit positions 48-63 contain a 16-bit
binary value indicating the length in
bytes of the longest machine-check
extended logout (MCEL) that can be
stored by the CPU. Special Conditions
The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized. Condition Code: unchanged.
The code remains Program Exceptions:
Access (store, operand 2)
Privileged operation
Specification Programming Notes 1. The program should
possibility that the
cation number may
digits A-F as well 0-9. allow for the CPU identifi­
contain the
as the digits
2. The principal uses of the informa­
tion stored by STORE CPU ID are the
following:
a. The CPU identification number,
in conjunction with the model
number, provides a unique CPU identification that can be used
in associating results with an
individual system, particularly
in regard to functional differ­
ences, performance differences,
and error handling.
b. The model number, in conjunc­
tion with the version code, can
be used by model-independent
programs in determining which
model-dependent recovery
programs should be called.
c. The MCEL length can be used by
model-independent programs to
allocate main storage for the MCEL area. STORE CPU TIMER [S] 'B209' o 16 20 31
The current value of the CPU timer is
stored at the doubleword location desig­
nated by the second-operand address.
Zeros are provided for the rightmost bit
positions that are not updated by the CPU timer. Special Conditions
The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized. Condition Code: unchanged. Program Exceptions:
The code
Access (store, operand 2)
remains
Operation (if the CPU-timer and
clock-comparator facility is
not installed) Privileged operation
Specification STORE PREFIX STPX [S] 'B211'
o 16 20 31
The contents of the prefix register are
stored at the word location designated
by the second-operand address. Zeros
are provided for bit positions 0-7 and 20-31. Special Conditions The operand must be designated on a word
boundary; otherwise, a specification
exception is recognized. Condition unchanged. Code: The code remains Chapter 10. Control Instructions 10-49

Program Exceptions:
Access (store, operand 2) Operation (if the multiprocessing
facility is not installed)
Privileged operation
Specification STORE THEN AND SYSTEM MASK STNSM D
1 (B
1 ),I
2 [51] 'AC'
o 8 16 20 31
Bits 0-7 of the current PSW are stored
at the first-operand location. Then the
contents of bit positions 0-7 of the
current PSW are replaced by the logical
AND of their original contents and the
second operand.
Special Conditions
The operation is suppressed on address­
ing and protection exceptions.
Condition Code:
unchanged. Program Exceptions:
The code
Access (store, operand 1)
remains
Operation (if the translation
facility is not installed) Privileged operation Programming Note STORE THEN AND SYSTEM MASK permits the
program to set selected bits in the
system mask to zeros while retaining the
original contents for later restoration.
For example, it may be necessary that a
program, which has no record of the
present status, disable program-event
recording for a few instructions. STORE THEN OR SYSTEM MASK STOSM D
1 (B
1 ),I
2
[SI]
'AD' 12 o 8 16 20 31
Bits 0-7 of the current PSW are stored
at the first-operand location. Then the
contents of bit positions 0-7 of the 10-50 System/370 Principles of Operation
current PSW are replaced by the logical OR of their original contents and the
second operand.
Special Conditions
The value to be loaded into the PSW is not checked for validity before loading.
However, immediately after loading, a
specification exception is recognized,
and a program interruption occurs, if the CPU is in the EC mode and the
contents of bit positions 0 and 2-4 of
the PSWare not all zeros. In this
case, the instruction is completed, and
the instruction-length code is set to 2.
The specification exception, which is
listed as a program exception for this
instruction, is described in the section
"Early Exception Recognition" in Chapter 6, "Interruptions." This exception may
be considered as caused by execution of
this instruction or as occurring early
in the process of preparing to execute
the subsequent instruction.
The operation is suppressed on address­
ing and protection exceptions.
Condition Code:
unchanged.
Program Exceptions:
The code
Access (store, operand 1)
remains
Operation (if the translation
facility is not installed) Privileged operation
Specification Programming Note STORE THEN OR SYSTEM MASK permits the
program to set selected bits in the
system mask to ones while retaining the
original contents for later restoration.
For example, the program may enable the CPU for I/O interruptions without having
available the current status of the
external-mask bit.
TEST BLOCK TB R I' R2 [RRE]
'B22C'
o 16 24 28 31
The storage locations and storage keys
of a 4K-byte block are tested for
usability, and the result of the test is
indicated in the condition code. The
test for usability is based on the