lation when DAT is on. When OAT is on
and the first-operand address cannot be
translated because of a situation that
would normally cause a page-translation
or segment-translation exception, the
instruction is completed by setting
condition code 3. When translation of the first-operand
address can be completed, or when OAT is
off, the storage key for the block
designated by the first-operand address is tested against the access key speci­
fied in bits 24-27 of the second-operand
address, and the condition code is set
to indicate whether store and fetch
accesses are permitted, taking into
consideration all applicable protection
mechanisms. Thus, for example, if the
low-address-protection facility is
installed and active and if the first­
operand effective address is less than
512, then a store access is not permit­
ted. Segment protection, when
installed, is also taken into account.
The contents of storage, including the
change bit, are not affected. Depending
on the model, the reference bit for the
first-operand address may be set to one,
even for the case in which the location
is protected against fetching. Special Conditions When OAT is on, an addressing exception
is recognized when the address of the
segment-table entry, the page-table
entry, or the operand real address after
translation designates a location which
is not available in the configuration.
Also, when DAT is on, a translation­
specification exception is recognized
when the segment-table entry or page­
table entry has a format error. When
DAT is off, only the addressing excep­
tion due to the operand real address
applies. For all of these cases, the
operation is suppressed.
Resulting Condition Code:
o Fetching permitted; storing
permitted
1 Fetching permitted; storing not
permitted
2 Fetching not permitted; storing
not permitted
3 Translation not available
Program Exceptions:
Addressing (operand 1) Operation (if the extended facility
is not installed)
Privileged operation
Translation specification
Programming 1. TEST PROTECTION permits a program
to check the validity of an address
passed from a calling program with­
out incurring program exceptions.
The instruction sets a condition
code to indicate whether fetching
or storing is permitted at the
location designated by the first­
operand address of the instruction.
The instruction takes into consid­
eration all of the protection
mechanisms installed in the
machine: key-controlled, segment,
and low-address protection. Addi­
tionally, since segment translation
and page translation may be a
program substitute for a protection
violation, these situations are
used to set the condition code
rather than cause a program excep­
tion.
2. See the programming notes under SET PSW KEY FROM ADDRESS for more
details and for an alternative
approach to testing validity of
addresses passed by a calling
program. The approach using TEST PROTECTION has the advantage of a
test which does not result in
interruptions; however, the test
and use are separated in time and
may not be accurate if the possi­
bility exists that the storage key
of the location in question can
change between the time it is test­
ed and the time it is used.
3. In the handling of dynamic address
translation, TEST PROTECTION is
similar to LOAD REAL ADDRESS in
that the instructions do not cause
page-translation and segment­
translation exceptions. Instead,
these situations are indicated by
means of a condition-code setting. Situations which result in condi­
tion codes 1, 2, and 3 for LOAD REAL ADDRESS result in condition
code 3 for TEST PROTECTION. The
instructions also differ in several
other respects. The address of TEST PROTECTION is a
logical address and thus is not
subject to translation when DAT is
off. The second-operand address of
LOAD REAL ADDRESS is a· virtual
address which is always translated. TEST PROTECTION may use the TLB for
translation of the address, whereas LOAD REAL ADDRESS does not use the
TLB. (LOAD REAL ADDRESS is the
only instruction which must perform
translation without use of the
TLB.)
When DAT is off for LOAD REAL ADDRESS, the translation-specifica­
tion exception for an invalid value
of bits 8-12 of control register 0 occurs after instruction fetching Chapter 10. Control Instructions 10-53

as part of the execution portion of
the instruction. This situation
cannot occur for TEST PROTECTION since the operand address is a logical· address and does not result in examination of control register
o when OAT is off. When OAT is on,
the exception would be recognized during instruction fetching. Since
the instruction-fetching portion of
an instruction is common for all
instructions, descriptions of
access exceptions associated with
instruction fetching do not appear
in the individual instruction defi­
nitions.
WRITE DIRECT WRD [51]
'84' Bt Dt
o 8 16 20 31
The byte at the location designated by
the first-operand address is made avail­
able as a set of direct-out static
signals. Eight instruction bits are
made available as signal-out timing
signals. When INVALIDATE PAGE TABLE ENTRY is not
installed, the first-operand address is a logical address and subject to normal
access exceptions. When INVALIDATE PAGE
TABLE ENTRY is installed, the first­
operand address is a real address and
therefore not subject to translation; 10-54 System/370 Principles of Operation
only addressing and key-controlled­
protection exceptions apply.
The eight data bits of the byte fetched
from the real storage location desig­
nated by the first-operand address are
presented on a set of eight direct-out lines as static signals. These signals
remain until WRITE DIRECT is again
executed. No checking bits are
presented with the eight data bits.
The contents of the 12 field are made
available simultaneously on a set of
eight signal-out lines as D.S-micro­
second to 1.O-microsecond timing
signals. On a ninth line (write out), a
D.S-microsecond to 1.O-microsecond
timing signal is made available concur­
rently with these timing signals. The
eight signal-out lines are also used in
the READ DIRECT instruction. No check­
ing bits are made available with the eight instruction bits.
A serialization function is performed
before the operand is fetched and again
after the signals have been presented. Condition Code:
unchanged.
Program Exceptions:
The code remains
Access (fetch, operand 1; access
applies only if the INVALIDATE
PAGE TABLE ENTRY instruction is
not installed)
Addressing (fetch, operand 1)
Operation (if the direct-control
facility is not installed)
Privileged operation
Protection (fetch, operand 1)