Information Stored (Fetched) Old PSW New PSW (fetched)
Machine-cheek-interruption code
Register-save areasCPU timer Clock comparator
Floating-point registers0, 2, 4, 6
General registers 0-15Control registers 0-15
Extended interruption information
External-damage code
Failing-storage address
Region code
logout areas
Fixed logout
Machine-check extended logout(MCEL) Explanation: * All locations are in real storage.
Starting Length
Location* in Bytes
48
112
232
216
224
352
384
448
244
248
252
256
Note 1
8
8
8
8
832 64
64
4
4
4
96
Note 2
1. The starting location of theMCEL is determined by the MCEL address in control register 15.
2. The length of theMCEL is model-dependent.
Machine-Cheek-Interruption locations
If the machine-cheek-interruption code
cannot be stored successfully or the newPSW cannot be fetched successfully, the CPU enters the check-stop state if the
check-stop-control bit is one.
A repressible machine-check condition
can initiate a machine-check inter
ruption only if bothPSW bit 13 is one
and the associated subclass mask bit in
control register 14 is also one. When
it occurs, the interruption does not
terminate the execution of the current
instruction; the interruption is taken
at a normal point of interruption, and
no program or supervisor-call inter
ruptions are eliminated. If the machine
check occurs during the execution of a
machine function, such as aCPU-timer update, the machine-check interruption
takes place after the machine function
has been completed.
When theCPU is disabled for a partic
ular repressible machine-check
condition, the condition remains
pending. Depending on the model and the
condition, multiple repressible condi
tions may be held pending for a
particular subclass, or only one condi
tion may be held pending for a
particular subclass, regardless of the
number of conditions that may have been
detected for that subclass. When multi
ple external-damage conditions occur,
each condition is retained.
When a repressible machine-check inter
ruption occurs because the interruption
condition is in a subclass for which theCPU is enabled, pending conditions in
other subclasses may also be indicated
in the same interruption code, even
though theCPU is disabled for those
subclasses. All indicated conditions
are then cleared.
If a machine check which is to be
reported as a system-recovery condition
is detected during the execution of the
interruption procedure due to a previous
machine-check condition, the system
recovery condition may be combined with
the other conditions, discarded, or held
pending.
An exigent machine-check condition can
cause a machine-check interruption only
whenPSW bit 13 is one. When a nullify
ing exigent condition causes a machine
check interruption, the interruption is
taken at a normal point of interruption.
When a terminating exigent condition
causes a machine-check interruption, the
interruption terminates the execution of
the current instruction and may elimi
nate the program and supervisor-call
interruptions, if any, that would have
occurred if execution had continued.
Proper execution of the interruption
sequence, including the storing of the
oldPSW and other information, depends
on the nature of the malfunction.When an exigent machine-check condition
occurs during the execution ofa machine
function, suchas a CPU-timer update,
the sequenceis not necessarily
completed.Chapter 11. Machine-Check Handling 11-13
Machine-cheek-interruption code
Register-save areas
Floating-point registers
General registers 0-15
Extended interruption information
External-damage code
Failing-storage address
Region code
logout areas
Fixed logout
Machine-check extended logout
Starting Length
Location* in Bytes
48
112
232
216
224
352
384
448
244
248
252
256
Note 1
8
8
8
8
8
64
4
4
4
96
Note 2
1. The starting location of the
2. The length of the
Machine-Cheek-Interruption locations
If the machine-cheek-interruption code
cannot be stored successfully or the new
check-stop-control bit is one.
A repressible machine-check condition
can initiate a machine-check inter
ruption only if both
and the associated subclass mask bit in
control register 14 is also one. When
it occurs, the interruption does not
terminate the execution of the current
instruction; the interruption is taken
at a normal point of interruption, and
no program or supervisor-call inter
ruptions are eliminated. If the machine
check occurs during the execution of a
machine function, such as a
takes place after the machine function
has been completed.
When the
ular repressible machine-check
condition, the condition remains
pending. Depending on the model and the
condition, multiple repressible condi
tions may be held pending for a
particular subclass, or only one condi
tion may be held pending for a
particular subclass, regardless of the
number of conditions that may have been
detected for that subclass. When multi
ple external-damage conditions occur,
each condition is retained.
When a repressible machine-check inter
ruption occurs because the interruption
condition is in a subclass for which the
other subclasses may also be indicated
in the same interruption code, even
though the
subclasses. All indicated conditions
are then cleared.
If a machine check which is to be
reported as a system-recovery condition
is detected during the execution of the
interruption procedure due to a previous
machine-check condition, the system
recovery condition may be combined with
the other conditions, discarded, or held
pending.
An exigent machine-check condition can
cause a machine-check interruption only
when
ing exigent condition causes a machine
check interruption, the interruption is
taken at a normal point of interruption.
When a terminating exigent condition
causes a machine-check interruption, the
interruption terminates the execution of
the current instruction and may elimi
nate the program and supervisor-call
interruptions, if any, that would have
occurred if execution had continued.
Proper execution of the interruption
sequence, including the storing of the
old
on the nature of the malfunction.
occurs during the execution of
function, such
the sequence
completed.