the instruction address, are unpredict­
able. Thus the validity bits associated
with fields which are due to be changed
by the instruction stream are meaning­
less when a terminating exigent
machine-check condition is reported.
When the point of interruption and the
point of damage due to an exigent machine-check condition are separated by
a checkpoint-synchronization function,
the damage has not been isolated to a
particular program, and system damage is
indicated.
Programming Note
When an exigent machine-cheek-interrup­
tion condition occurs, the point of
interruption which is chosen affects the
amount of damage which must be
indicated. An attempt is made, when
possible, to choose a point of interrup­
tion which permits the minimum
indication of damage. In general, the
preference is the interruption point
immediately preceding the error.
When all the status information stored
as a result of an exigent machine­
check-interruption condition does not
reflect the same point, an attempt is
made when possible to choose the point
of interruption so that the instruction
address which is stored in the machine­
check old PSW is valid. MACHINE-CHECK-INTERRUPTION CODE On all machine-check interruptions, a
machine-cheek-interruption code (MCIC) is stored at the doubleword starting at
real location 232 and has the format
shown in the figure "Machine-Check
Interruption-Code Format."
Bits in the MCIC which are not assigned,
or not implemented by a particular
model, are stored as zeros. Chapter 11. Machine-Check Handling 11-15

S P S T
D D R D 0 I 10 I 10 32
o
1
2
3
4
5
6
7
8 10 13
14
15
16
17
18
19 20 21
22
23
24
25
26
27
28
29 30 31
32
34
46
47
34
48-63
C E V S S K D W M P I F R E
D D F E C E S P S M A A C C
8 10 13 16 24 000 010 000 0 oli gl MCEL Length 40 46 48
System damage (SD)
Instruction-processing damage (PD)
System recovery (SR)
Interval-timer damage (TD)
Timing-facility damage (CD)
External damage (ED)
Vector-facility failure (VF)
Degradation (DG)
Warning (W)
Service-processor damage (SP)
Vector-facility source (VS)
Backed up (B)
Delayed (D)
Storage error uncorrected (SE)
Storage error corrected (SC)
Storage-key error uncorrected (KE)
Storage degradation (OS) PSW-EMWP validity (WP) PSW mask and key validity (MS)
F
P PSW program-mask and condition-code validity (PM)
PSW-instruction-address validity (IA)
Failing-storage-address validity (FA)
Region-code validity (RC)
External-damage-code validity (EC)
Floating-point-register validity (FP)
General-register validity (GR)
Control-register validity (CR)
Logout validity (LG)
Storage logical validity (ST)
Indirect storage error (IE)
Delayed-access exception (DA)
CPU-timer validity (CT)
Clock-comparator validity (CC)
Machine-check-extended-logout (MCEL) length
G C L S R R G T
31
63
Note: All other bits of the MCIC are unassigned and stored as zeros.
Machine-Check Interruption-Code Format SUBCLASS Bits 0-8 and 10 are the subclass bits
which identify the type of machine-check
condition causing the interruption. At
least one of the subclass bits is stored
as a one. When multiple errors have
occurred, several subclass bits may be
set to ones.
11-16 System/370 Principles of Operation
System Damage
Bit 0 (SD), when one, indicates that
damage has occurred which cannot be
isolated to one or more of the less
severe machine-check subclasses. When
system damage is indicated, the remain­
ing bits in the machine-check­
interruption code are not meaningful,
and information stored in the register­
save areas and machine-check extended­
interruption fields is not meaningful. System damage is a terminating exigent
condition and has no subclass-mask bit.