and (3) when channel-set switching is
installed, may be presented even when
the channel set is disconnected. In
some models, external secondary reports
due to I/O and channel errors may be
broadcast to all CPUs in the configura­
tion.
The third use of external secondary
report is to provide a mechanism for
presenting logout information associated
with errors detected by other external
devices or during operator-initiated
operations. The primary indication in
this case is normally by means of the
external device or by an indication to
the operator. Channel Not Operational (CN): Bit 3,
when one, indicates that one or more
channels in the configuration have
entered the not-operational state with­
out signaling system reset to their
attached devices. This situation occurs
when these channels have detected an
error of such severity that channel
operations cannot continue. In config­
urations with channel-set switching,
channel-not-operational conditions are
reported to all CPUs in the configura­
tion even when the channel set is
disconnected. Only those state changes
in the channel which would be seen if
the channel set were connected to a CPU are considered for purposes of this
interruption. The channel-not­
operational condition is reported only
in configurations in which all channels have implemented the recovery-extension
facility. Channel-Control Failure (CC): Bit 4,
when one, indicates that-one or more
channels in the configuration have
entered the not-operational state and
mayor may not have signaled system
reset to their attached devices. This
situation occurs when the channels have
lost power or detected an error of such
severity that channel operations cannot
continue. In configurations with
channel-set switching, channel-control­
failure conditions are reported to all CPUs in the configuration, even when the
channel set is disconnected. The
channel-control-failure condition is
reported only in configurations in which
all channels have implemented the
recovery-extension facility.
When the machine can determine that all
affected channels actually entered the
not-operational state without signaling
system reset to their attached devices,
the channel-not-operational condition is
indicated rather than channel-control
failure.
I/O-Instruction Timeout (ST): Bit 5,
when one, indicates that the execution
time of an I/O instruction has exceeded
the maximum allowed by the CPU. The I/O instruction has been completed by
setting condition code 3. When the CPU is enabled for external-damage machine­
check conditions at the time the timeout
occurs, and, if a program interruption
for a PER event does not intervene, the
instruction address stored in the
machine-check old PSW (if indicated as
valid) points to the instruction follow­
ing the last executed I/O instruction.
In this case, the address of the failing I/O instruction (or of EXECUTE) can be
obtained by subtracting 4 from the
instruction address. Timeout of an I/O instruction is reported by means of bit
5 only when the CPU can ensure that the
channel has not signaled system reset to
its attached devices. Depending on the
channel and the timeout condition, the
channel mayor may not be operational.
The I/O-instruction-timeout condition is
reported only in configurations in which
all channels have implemented the
recovery-extension facility. 1/0- I n t err u p t ion Timeout ( T T) : Bit 6 , when one, indicates that the channel
portion of an I/O interruption has
exceeded the time limit established by
the CPU and that the CPU has canceled
the interruption. The I/O-interruption
condition mayor may not have been lost,
and information mayor may not have been
stored at the locations of the old PSW, CSW, and other areas associated with an I/O interruption. The I/O interruption
was not taken; that is, sequenti al instruction processing continued without
loading the I/O new PSW. Timeout of an I/O interruption is reported by means of
bit 6 only when the CPU can ensure that
the channel has not signaled system
reset to its attached devices. Depend­
ing on the channel and the timeout
condition, the channel mayor may not be
operational. The I/O-interruption­
timeout condition is reported only in
configurations in which all channels
have implemented the recovery-extension
facility.
Expanded storage Not Operational (XN):
Bit 8, when one, indicates that the
controller associated with some or all
of the expanded storage in the config­
uration has become not operational.
Expanded-storage-not-operational
tions are reported to all CPUs configuration.
condi­
in the
Expanded-storage Control Failure (XF):
Bit 9, when one, indicates a
malfunction has been detected in a
controller associated with some or all
of the expanded storage in the config­
uration. When expanded-storage control
failure is indicated, the blocks of the
expanded storage contain either the
proper contents or a preserved error.
Expanded-storage-control-failure
tions are reported to all CPUs configuration.
condi­
in the Chapter 11. Machine-Check Handling 11-25

Reserved: Bits 0, I, 7, and 10-31 are
reserved for future expansion and are
always set to zeros.
Programming Notes
1. Bit 0 is reserved for future expan­
sion and possible redefinition of
the remaining bits in the
external-damage code. Thus, the
program should test bit 0 for a
zero value before interpreting the
other bits in the external-damage
code.
2. Bit 3 (channel not operational),
bit 4 (channel-control failure),
and external damage with the
external-damage code invalid, form a set of three errors of increasing
severity. When a channel-not­
operational or channel-control­
failure condition is reported, the
affected channels enter the not­
operational state. Thus, if the
program is aware of the channel
addresses of all channels which have been operational in the
configuration, then, by repeatedly
executing the TEST CHANNEL instruc­
tion designating each channel in
the configuration, the program can
determine which channels have
entered the not-operational state.
Since the channel-not-operational
and channel-control-failure condi­
tions are reported to all CPUs in
the configuration, all channels on
all CPUs must be tested. When
channel-set switching is installed,
then all channels, including those
not currently connected to any CPU, must be tested.
Channel not operational is the
least severe indication of the
three. The affected channels can
be determined as indicated above,
and it is known in this case that
system reset has not been signaled
to the attached devices.
Channel-control failure is more
severe than channel not operational
in that system reset may have been
signaled to the attached devices.
External damage with the external­
damage code invalid is the most
severe indication of the three.
All channels in the configuration
may have been affected, and the
affected channels mayor may not
appear to be not operational when a
TEST CHANNEL instruction is
executed. Damage which can be
reported by means of this indi­
cation includes errors occurring
during the execution of an I/O
11-26 System/370 Principles of Operation
interruption. For example, this indication can be used to report
that an I/O interruption occurred
with incorrect I/O address, incor­
rect CSW, incorrect full-channel
logout, incorrect limited-channel­
logout information, or channel­
control failure.
3. On some models, a channel which has
become channel not operational may
be restored by executing CLEAR
CHANNEL. See the programming note
under "CLEAR CHANNEL," in Chapter
13, Input/Output Operations."
FAILING-STORAGE ADDRESS
When storage error uncorrected, storage
error corrected, or storage-key error
uncorrected is indicated in the
machine-check-interruption code, the
associated address, called the failing­
storage address, is stored in bit posi­
tions 8-31 of the word at real location
248. Bits 0-7 of that word are set to
zeros. When the extended-rea I-address
facility is installed, the failing­
storage address is 31 bits, and a zero
is stored in bit position 0 of the word
at real location 248. The field is
valid only if the failing-storage­
address validity bit, bit 24 of the
machine-check-interruption code, is one.
In the case of storage errors, the
failing-storage address may designate
any byte within the checking block. For
storage-key error uncorrected, the
failing-storage address may designate
any address within the block of storage
associated with the storage key that is
in error. When an error is detected in
more than one location before the inter­
ruption, the failing-storage address may
designate any of the failing locations.
The address stored is an absolute
address; that is, the value stored is
the address that is used to reference
storage after dynamic address trans­
lation and prefixing have been applied.
REGION CODE
Depending on the model, a region code
may be stored in the word at real
location 252. The field is valid only
if the region-code-validity bit, bit 25
in the machine-check-interruption code,
is one. The region code may contain
model-dependent information which more
specifically defines the location of the
error. For example, it may contain a
model-dependent address of the unit
causing an external damage or recovery
report.