General-Register Validity
Bit 28 (GR), when one, indicates that
the contents of the general-register
save area at real locations 384-447
reflect the correct state of the general
registers at the point of interruption.
Control-Register Validity
Bit 29 (CR), when one, indicates that
the contents of the control-register
save area at real locations 448-511
reflect the correct state of the control
registers at the point of interruption.
Logout Validity
Bit 30 (LG), when one, indicates that
the machine-check extended-logout infor­
mation was correctly stored. When a
model does not provide extended-logout
information, bit 30 is set to zero.
storage Logical Validity
Bit 31 (ST), when one, indicates that
the storage locations, the contents of
which are modified by the instructions
being executed, contain the correct
information relative to the point of
interruption. That is, all stores
before the point of interruption are
completed, and all stores, if any, after
the point of interruption are
suppressed. When a store before the
point of interruption is suppressed
because of an invalid CBC, the storage­
logical-validity bit may be indicated as
one, provided that the invalid CBC has
been preserved as invalid.
When instruction-processing damage is
indicated but processing backup is not
indicated, the storage-Iogical-validity
bit has no meaning.
Storage logical validity reflects only
the instruction-processing activity and
does not reflect errors in the state of
storage as the result of interval-timer
update or I/O operations, or of the
storing of the old PSW and other inter­
ruption information. CPU-Timer Validity
Bit 46 (CT), when one, indicates that
the CPU timer is not in error and that
the contents of the CPU-timer save area
at real location 216 reflect the correct
state of the CPU timer at the time the
interruption occurred. When the CPU-timer and clock-comparator facility
is not installed, bit 46 is set to zero. Clock-Comparator Validity
Bit 47 (CC), when one, indicates that
the clock comparator is not in error and
that the contents of the clock­
comparator save area at real location
224 reflect the correct state of the
clock comparator. When the CPU-timer and clock-comparator facility is not
installed, bit 47 is set to zero.
Programming Note
The validity bits must be used in
conjunction with the subclass bits and
the backed-up bit in order to determine
the extent of the damage caused by a
machine-check condition. No damage has
occurred to the system when all of the
following are true: • • • • The four PSW-validity bits, the
three register-validity bits, the
two timing-facility-validity bits,
and the storage-Iogical-validity
bit are all ones if the facility
with which they are associated is
installed.
Subclass bits 0, 3, 4, 5, 6, and 10 are zeros.
The instruction-processing-damage
bi tis zero or, if one, the
backed-up bit is also one.
The vector-facility-source bit and
the delayed-access-exception bit
are zeros.
Machine-Check Extended-Logout Length
Bits 48-63 of the machine-check­
interruption code contain a 16-bit bina­
ry value indicating the length in bytes
of the information most recently stored
in the extended-logout area, starting at
the real location designated by the
machine-check extended-logout address in
control register 15. When no extended
logout has occurred, this field is set
to zero.
Programming Note
When asynchronous machine-check extended
logouts are permitted (control register Chapter 11. Machine-Check Handling 11-23

14, bit 8, is one), more than one extended logout may have occurred. The
length stored on interruption does not
necessarily indicate the longest logout
which has occurred. MACHINE-CHECK EXTENDED INTERRUPTION INFORMATION As part of the machine-check inter­
ruption, in some cases, extended inter­
ruption information is placed in fixed
areas assigned in storage. The contents
of registers associated with the CPU are placed in register-save areas. For
external damage, additional information
is provided for some models by storing
an external-damage code. When storage
error uncorrected, storage error
corrected, or storage-key error uncor­
rected is indicated, the failing-storage
address is saved. Some models store a
region code to show the location of the
error.
Each of these fields has associated with
it a validity bit in the machine-check­
interruption code. If, for any reason,
the machine cannot store the proper
information in the field, the associated
validity bit is set to zero. REGISTER-SAVE AREAS As part of the machine-check inter­
ruption, the current contents of the CPU
registers, except for the prefix regis­
ter and the TOO clock, are stored in
five register-save areas assigned in
storage. Each of these areas has asso­
ciated with it a validity bit in the
machine-cheek-interruption code. If,
for any reason, the machine cannot store
the proper information in the field, the
associated validity bit is set to zero.
The following are the five sets of
registers and the real locations in
storage where their contents are saved
during a machine-check interruption.
locations
216-223
224-231
352-383
384-447
448-511
Registers CPU timer Clock comparator
Floating-point regis-
ters 0, 2, 4, 6
General registers 0-15 . Control registers 0-15 When the CPU-timer and clock-comparator
facility or the floating-point facility
is not installed, the corresponding
locations remain unchanged. The infor­
mation stored for unassigned or unin­
stalled control-register positions is
unpredictable.
11-24 System/370 Principles of Operation EXTERNAL-DAMAGE CODE The word at real location 244 is the
external-damage code. This field, when
implemented and indicated as valid,
describes the cause of external damage.
The field is valid only when the
external-damage bit and the external­
damage-validity bit (bits 5 and 26 in
the machine-cheek-interruption code) are
both ones. The presence and extent of
reporting an external-damage code depend
on the model.
The external-damage code has the follow-
ing format: 10 C C S N C T 0 2 7 8 10 31
External Secondary Report (ES): Bit 2,
when one, indicates that the machine­
check interruption has been reported for
an external error for which the primary
indication has been or will be made by
means of some other report. The primary
indication may be an I/O-error
condition, an indication to the
operator, another machine-check inter­
ruption, or even another bit in the same
machine-check interruption.
External secondary report has three main
purposes. First, it is used to present
the failing-storage address associated
with storage errors detected during
channel accesses to storage. In this
case, the failing-storage address and
storage-error-uncorrected, storage­
error-corrected, or storage-key-error­
uncorrected indication are used to
identify the cause of failure and the
associated location. Second, external secondary report is
used to present model-dependent logout
information for an error associated with
a channel that is physically integrated
with the CPU. The machine-check indi­
cation in this case is provided so that
channels integrated with the CPU can use
the normal CPU logout mechanism for
presenting the model-dependent logout
information.
For these two purposes, the primary
error indication is normally by means of
an I/O-error condition. These errors
include conditions presented as
channel-control check, channel-data
check, and interface-control check.
External secondary reports due to I/O and channel errors (1) may be presented
to any or all CPUs in the configuration,
(2) are not necessarily presented to the
CPU to which the channel is connected,