When the access to storage is for the
purpose of channel-program execution,
the subchannel key associated with the I/O operation is the access key. The
subchannel key is specified for an I/O operation in bit positions 0-3 of the
channel-address word (CAW); the subchan­
nel key is later placed in bit positions 0-3 of the channel-status word (CSW) stored as a result of the I/O operation.
When a CPU access is prohibited because
of key-controlled protection, the unit
of operation is suppressed or the
instruction is terminated, and a program
interruption for a protection exception
takes place. When a channel-program
access is prohibited, protection check
is indicated in the CSW stored as a
result of the operation.
When a store access is prohibited
because of key-controlled protection,
the contents of the protected location
remain unchanged. When a fetch access
is prohibited, the protected information
is not loaded into a register, moved to
another storage location, or provided to
an I/O device. For a prohibited
instruction fetch, the instruction is
suppressed, and an arbitrary
instruction-length code is indicated.
Key-controlled protection is independent
of whether the CPU is in the problem or
the supervisor state and, except as
described below, does not depend on the ,type of CPU instruction or channel­
command word being executed. I \ , Except where otherwise specified, all
accesses to storage locations that are
explicitly designated by the program and
that are used by the CPU to store or
fetch information are subject to key­
controlled protection.
Accesses to the second operand of TEST BLOCK are not subject to key-controlled
protection.
All storage accesses by a channel to
fetch a CCW or IDAW or to access a data
area designated during the execution of
a CCW, are subject to key-controlled
protection. However, if a CCW, an IDAW,
or output data is prefetched, a protection check is not indicated until
the CCW or IDAW is due to take control
or until the data is due to be written.
Key-controlled protection is not applied
to accesses that are implicitly made for
any of such sequences as: • An interruption • Updating the interval timer • CPU logout • Fetching of table entries
dynamic-address translation,
for PC- • • • • • • • number translation, ASN transla­
tion, or ASN authorization
DAS tracing
A store-status function
Fetching the CAW during the
execution of an I/O instruction
Storing of the CSW by an I/O instruction or interruption
Storing channel identification
during the execution of STORE CHAN­ NEL ID
A limited channel logout
A full channel logout • Initial program loading
Similarly, protection does not apply to
accesses initiated via the operator
facilities for altering or displaying
information. However, when the program
explicitly designates these locations,
they are subject to protection.
SEGMENT PROTECTION The segment-protection facility controls
access to virtual storage by using the
segment-protection bit in each segment­
table entry. It provides protection
against improper storing.
The segment-protection bit, bit 29 of
the segment-table entry, controls wheth­ er storing is allowed into the corre­
sponding segment. When the bit is zero,
both fetching and storing are permitted;
when the bit is one, only fetching is
permitted. When an attempt is made to
store into a protected segment, a
program interruption for protection
takes place. The contents of the
protected location remain unchanged.
Segment protection applies to all
store-type references that use a virtual
address. LOW-ADDRESS PROTECTION The low-address-protection facility pro­
vides protection against the destruction
of main-storage information used by the CPU during interruption processing.
This is accomplished by prohibiting
instructions from storing with effective
addresses in the range 0 through 511. The range criterion is applied before
address transformation, if any, of the
address by dynamic address translation
or prefixing. Chapter 3. Storage 3-9

low-address protection is under control
of bit 3 of control register 0, the
low-address-protection-control bit.
When the bit is zero, low-address
protection is off; when the bit is one,
low-address protection is on.
If an access is prohibited because of
low-address protection, the contents of
the protected location remain unchanged, a program interruption for a protection
exception takes place, and the unit of
operation is suppressed or the instruc­
tion terminated.
Any attempt by the program to store by
using effective addresses in the range 0 through 511 is subject to low-address
protection. low-address protection is
applied to the store accesses of
instructions whose operand addresses are logical, virtual, or real. low-address
protection is also applied to the trace
table.
low-address protection is not applied to
accesses made by the CPU or channel for
such sequences as interruptions, updat­
ing the interval timer, CPU logout, and the initial-program-loading and store­
status functions, nor is it applied to data stores during I/O data transfer.
However, explicit stores by a program at any of these locations are subject to
low-address protection. Programming Note
Low-address protection
controlled protection apply
store accesses, except that: and key­
to the same • Low-address protection does not
apply to storing performed by a
channel, whereas key-controlled
protection does. • Key-controlled protection does not
apply to DAS tracing or the second
operand of TEST BLOCK, whereas
low-address protection does.
REFERENCE RECORDING
Reference recording provides information
for use in selecting pages for replace­
ment. Reference recording uses the
reference bit, bit 5 of the storage key.
A reference bit is provided in each
storage key when the dynamic-address­
translation facility is installed. The
reference bit is set to one each time a
location in the corresponding storage
block is referred to either for fetching
or storing information, regardless of
whether the CPU performing the access is
in the EC mode or BC mode or whether DAT
is on or off in that CPU. 3-10 System/370 Principles of Operation
Reference recording is always active and
takes place for all storage accesses,
including those made by any CPU, channel, or operator facility. It takes
place for implicit accesses made by the
machine, such as those which are part of
interruptions and I/O-instruction
execution.
Reference recording
operand accesses
instructions since
to a storage key
storage location:
does not occur for
of the following
they directly refer
without accessing a
INSERT STORAGE KEY INSERT STORAGE KEY EXTENDED
RESET REFERENCE BIT (reference bit
is set to zero)
RESET REFERENCE BIT EXTENDED (ref­
erence bit is set to zero)
SET STORAGE KEY (reference bit is
set to a specified value)
SET STORAGE KEY EXTENDED (reference
bit is set to a specified
value)
The record provided by the reference bit
is SUbstantially accurate. The refer­
ence bit may be set to one by fetching
data or instructions that are neither
designated nor used by the program, and, under certain conditions, a reference
may be made without the reference bit
being set to one. Under certain unusual
circumstances, a reference bit may be
set to zero by other than explicit
program action.
CHANGE RECORDING
Change recording provides information as
to which pages have to be saved in
auxiliary storage when they are replaced
in main storage. Change recording uses
the change bit, bit 6 of the storage
key. A change bit is provided in each
storage key when the dynamic-address­
translation facility is installed.
The change bit is set to one each time a store access causes the contents in the
corresponding storage block to be
changed. A store access that does not
change the contents of storage mayor
may not set the change bit to one.
The change bit is not set to one for an
attempt to store if the access is
prohibited. In particular:
1. For the CPU, a store access is prohibited whenever an access
exception exists for that access,
or whenever an exception exists
which is of higher priority than
the priority of an access exception
for that access.