2. For a channel, a store access is prohibited whenever a key-
controlled-protection violation
exists for that access.
Change recording is always active and
takes place for all store accesses to
storage, including those made by any CPU, channel, or operator facility. It
takes place for implicit references made
by the machine, such as those which are
part of interruptions.
Change recording does not take place for
the operands of the following
instructions since they directly modify
a storage key without modifying a stor­
age location:
RESET REFERENCE BIT
RESET REFERENCE BIT EXTENDED
SET STORAGE KEY (change bit is set
to a specified value)
SET STORAGE KEY EXTENDED (change
bit is set to a specified
value)
Change bits which have been changed from
zeros to ones are not necessarily
restored to zeros on CPU retry (see the
section "CPU Retry" in Chapter 11,
"Machine-Check Handling"). See the
section "Exceptions to Nullification and
Suppression" in Chapter 5, "Program Execution," for a description of the
handling of the change bit in certain
unusual situations. PREFIXING Prefixing provides the ability to assign
the range of real addresses 0-4095 (the
prefix area) to a different block in
absolute storage for each CPU, thus
permitting more than one CPU sharing
main storage to operate concurrently
with a minimum of interference, espe­
cially in the processing of
interruptions. Prefixing is provided as
part of the multiprocessing facility. Prefixing causes real addresses in the
range 0-4095 to correspond to the block
of 4K absolute addresses identified by
the value in the prefix register for the CPU, and the block of real addresses
identified by the value in the prefix
register to correspond to absolute
addresses 0-4095. The remaining real
addresses are the same as the corre­
sponding absolute addresses. This
transformation allows each CPU to access
all of main storage, including the first
4K bytes and the locations designated by
the prefix registers of other CPUs. The relationship between real and abso­
lute addresses is graphically depicted
in the figure "Relationship between Real
and Absolute Addresses."
The prefix is a 19-bit quantity
contained in bit positions 1-19 of the
prefix register. Bits 1-7 of the prefix
register are always zeros. The register
has the following format: 1////////////1 018 20 31
The contents of the register can be set
and inspected by the privileged
instructions SET PREFIX and STORE PREFIX, respectively. On setting, bits
corresponding to bit positions 0-7 and 20-31 of the prefix register are
ignored. On storing, zeros are provided
for these bit positions. When the
contents of the prefix register are
changed, the change is effective for the
next sequential instruction.
With the introduction of the storage­
key-instruction-extension facility, the
test-block facility, and the extended­
real-addressing facility, prefixing is
described in terms of 31-bit real
addresses, whether or not these facili­
ties are installed. All real addresses
are considered to be 31 bits, with any
shorter address fields extended to 31
bits by appending zeros on the left.
Thus, 24-bit real addresses are extended
to 31 bits by appending zeros on the
left.
When prefixing is applied, the real
address is transformed into an absolute
address by using one of the following
rules, depending on bits 1-19 of the
real address:
1. Bits 1-19 of the address, if all
zeros, are replaced with bits 1-19
of the prefix.
2. Bits 1-19 of the address, if equal
to bits 1-19 of the prefix, are
replaced with zeros.
3. Bits 1-19 of the address, if not
all zeros and not equal to bits
1-19 of the prefix, remain
unchanged.
In all cases, bits 20-31 of the address
remain unchanged. Only the address presented to storage is
translated by prefixing. The contents
of the source of the address remain
unchanged.
The distinction between real and abso­
lute addresses is made even when the
prefix register contains all zeros, in
which case a real address and its corre­
sponding absolute address are identical. Chapter 3. Storage 3-11
1 1 I I I I I l<J-----;-No Change-+-----+---- I ""Address 4096 LAddress I \ i Address I I __ L __________ I L ________ -.J ,...-Address 4096 _Address
o
o Real Addresses
for CPU A Absolute Addresses Real Addresses
for CPU B
(1) Real addresses in which bits 1-19 are equal to the prefix for this CPU (A or
B).
(2) Absolute addresses of the block that contains for this CPU (A or B) the real
locations 0-4095.
Relationship between Real and Absolute Addresses ADDRESS SPACES An address space is a consecutive
sequence of integer numbers (virtual
addresses), together with the specific
transformation parameters which allow each number to be associated with a byte
location in storage. The sequence starts at zero and proceeds left to
right. When a virtual address is used by a CPU to access main storage, it is first
converted, by means of dynamic address
translation (DAT), to a real address,
and then, by means of prefixing, to an
absolute address. OAT uses two levels
of tables (segment tables and page tables) as transformation parameters.
The designation (origin and length) of a
segment table is found for use by OAT in
a control register.
When DAS is not installed, the CPU can
translate virtual addresses belonging to
3-12 System/370 Principles of Operation
one address space --the primary address
space, which consists of prlmary virtual addresses. When DAS is installed, at
any instant the CPU can translate virtu­
al addresses of two address
spaces --the primary address space,
consisting of primary virtual addresses,
and the secondary address space,
consisting of secondary virtual
addresses. The segment table defining
the primary address space is specified
by control register 1 and that defining
the secondary address space by control
register 7.
With DAS, each address space is assigned
an address-space number (ASH). An ASH­ translation mechanism ;s provided with DAS, which, given an ASH, can locate (by
using a two-level table lookup) the
designation of the segment table which
defines the address space. Certain
instructions use ASH translation and
load the resulting segment-table desig­
nation into the appropriate control
register.
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