errors are indicated during START I/O,
and during START I/O FAST RELEASE when it is executed as START I/O, by the
condition-code setting and by the status
portion of the CSW. When the SIOF func­
tion is performed, the first two errors
are indicated as for START I/O, and the
remaining errors may be indicated as for SIO or may be indicated in a subsequent I/O interruption.
Depending on the model, conditions 9, 10, 11 and 12 may (a) cause an error
condition to be recognized and prevent
operation initiation or (b) may cause an
error condition to be recognized only if the operation causes the device to
attempt to transfer data. In case (b),
a command that specifies an immediate
operation does not cause an error indi­ cation for an SIO or SIOF function.
1. Invalid CCW-address specification
in CAW 2. Invalid CAW format
3. Invalid CCW address in CAW 4. First-CCW location protected
against fetching
5. First CCW specifying transfer in
channel
6. Invalid command code in first CCW 7. Invalid count in first CCW 8. Invalid format for first CCW 9. If channel indirect data addressing (CIDA) was specified, an invalid
data-address specification in the
first CCW 10. If CIDA was specified, an invalid
data address in the first CCW 11. If CIDA was specified, the first­
IDAW location protected against
fetching
12. If CIDA was specified, invalid
format for the first IDAW
13. If suspend control was specified,
invalid suspend flag in first CCW. The CSW indicates program check, except
for items 4 and 11, for which protection
check is indicated.
Device Error: Programming or equipment
errors detected by the device as part of
the execution of TEST I/O, START I/O, or
START I/O FAST RELEASE are indicated by
unit check or unit exception in the CSW. The causes of unit check and unit excep­
tion for each type of I/O device are
detailed in the SL pUblication for the
device. INSTRUCTION FORMATS
All I/O instructions use the following S format: Op Code o 16 20 31
Except for STORE CHANNEL 10, bit posi­
tions 8-14 of these instructions are
ignored unless the system model provides
the suspend-and-resume facility. When
the facility is provided, bits 8-14 are
ignored, except for RESUME I/O, STORE CHANNEL 10, and the operation codes 9C03 through 9CFF, which are invalid.
The second-operand address specified by
the B2 and O 2 fields is not used to
designate data but instead is used to
identify the channel and I/O device.
Address computation follows the rules of
address arithmetic. The effective
address has the following format: I////////Ichn AddrlDev Addrl 8 16 24 31
Bit positions
I/O address.
ignored. INSTRUCTIONS 16-31 contain the 16-bit
Bit positions 8-15 are
All I/O instructions cause a serializa­
tion and checkpoint-synchronization
function to be performed. See the
section "Serialization" in Chapter 5,
"Program Execution."
The names, mnemonics, and operation
codes of the I/O instructions are listed
in the figure "Summary of Input/Output
Instructions." The figure also indi­
cates that all I/O instructions cause a
program interruption when they are encountered in the problem state, that
all I/O instructions set the condition
code, and that all I/O instructions are
in the S instruction format.
Note: In the detailed descriptions of
the individual instructions, the mnemon­
ic and the symbolic operand designation
for the assembler language are shown
with each instruction. In the case of
START I/O, for example, SIO is the
mnemonic and D 2 (B 2 ) the operand desig­
nation. Chapter 13. Input/Output Operations 13-15

Mne- Op* Name monic Characteristics Code CLEAR CHANNEL CLRCH 5 C RE P ¢ 9F01 CLEAR I/O CLRIO S C P ¢ 9001 HALT DEVICE HDV 5 C P ¢ 9E01 HALT I/O HIO S C P ¢ 9EOO RESUME I/O RIO S C SR P ¢ 9C02 START I/O 510 5 C P ¢ 9COO START I/O FAST RELEASE SIOF 5 C P ¢ 9C01 STORE CHANNEL ID STIDC 5 C P ¢ B203 TEST CHANNEL TCH 5 C P ¢ 9FOO TEST I/O TIO 5 C P ¢ 9DOO Explanation: ¢ Causes serialization and checkpoint synchronization. * The handling of bits 8-15 of the operation code depends on the
instruction and the facilities installed. See the description
of the instruction for details. C Condition code is set.
P Privileged-operation exception.
RE Recovery-extension facility.
5 5 instruction format.
SR Suspend-and-resume facility.
Summary of Input/Output Instructions
Programming Note
The instructions CLEAR I/O, HALT DEVICE, HALT I/O, START I/O, START I/O FAST
RELEASE, STORE CHANNEL ID, and TEST I/O may cause a CSW to be stored. To
prevent the contents of the CSW stored
by the instruction from being destroyed
by an immediately following I/O inter­
ruption, the CPU must be disabled for
all I/O interruptions before CLEAR I/O, HALT DEVICE, HALT I/O, START I/O, START I/O FAST RELEASE, STORE CHANNEL ID, or
TEST I/O is issued and must remain disa­
bled until the information in the CSW provided by any of these instructions
has been acted upon or stored elsewhere
for later use. CLEAR CHANNEL signaled to all I/O devices attached to
the addressed channel.
Bits 8-14 of the instruction are
ignored. Bits 16-23 of the second­
operand address identify the channel to
which the instruction applies. Bits
24-31 of the address are ignored.
The CLRCH function inspects only the
state of the addressed channel. When
the channel is available or
interruption-pending, I/O-system reset
is performed.
When the channel is working, some chan­
nels may indicate busy and cause no I/O-interface action, while other chan­
nels cause I/O-system reset to be
performed.
When the channel is not operational
because of a channel-cheek-stop condi­
tion, some channels cause an I/O-system reset to be performed on the I/O inter-
[5] face. In all other not-operational­
state cases, the reset function is
inhibited.
'9FOl'
o 16 20 31
With the recovery-extension facility
installed, the CLRCH function is
performed. Otherwise, the TCH function,
which is described in the definition of
TEST CHANNEL, is performed. I/O-system reset is performed in the
addressed channel, with system reset
13-16 System/370 Principles of Operation
Program Exceptions:
Privileged operation
Resulting Condition Code: o I/O-system reset was performed
on the I/O interface associated
with the addressed channel
1
2 Channel busy