operation. Thus, there is no
assurance that a CCW read as data
is valid until the operation is
completed. If the CCW is in error, the use of the CCW in the current
operation may cause subsequent data
to be placed in wrong storage
locations with resultant
destruction of the contents of
those locations.
2. When, during data chaining, an I/O device transfers data by using the
data-streaming facility (see the
section "Data-Streaming Feature" in Chapter 2 of the publication IBM System/360 and System/370 I/O Interface Channel to Control Unit
Original Eguipment--Manufacturer5' Information, GA22-6974), an overrun
or chaining-check condition may be
recognized when a small count value
is specified in the CCW. The mini­
mum acceptable number of bytes that
can be specified varies as a func­
tion of the system model and system
activity. Refer to the appropriate
channel SL pUblication to determine
the most reasonable minimum byte
count that can be handled by the
channel. Command Chaining During command chaining, the new CCW fetched by the channel specifies a new I/O operation. The channel fetches the
new CCW and initiates the new operation
(unless the new CCW contains a suspend
flag) upon receipt of the device-end
signal for the current operation. The
presence of a suspend flag in the new CCW causes command chaining to be termi­
nated. (See the section "Suspension of Channel-Program Execution" later in this
chapter.) When command chaining takes
place, the completion of the current
operation does not generate an inter­
ruption condition, and the count
indicating the amount of data trans­
ferred during the current operation is
not made available to the program. For
operations involving data transfer, the
new command always applies to the next
block at the device.
The new operation is initiated only if
no unusual situations have been detected
in the current operation. In
particular, the channel initiates a new I/O operation by command chaining upon
receipt of a status byte signaling one
of the following status combinations:
device end, device end and status modi­
fier, device end and channel end, device
end and channel end and status modifier.
In the former two cases, channel end
must have been signaled before device
end, with all other status bits set to
zeros. If status such as attention,
unit check, unit exception, incorrect
length, program check, or protection check has occurred, the sequence of
operations is concluded, and the status
associated with the current operation
causes an interruption condition to be
generated. The new CCW in this case is
not fetched. Incorrect length does not
suppress command chaining if the current CCW has the SLI flag set to one.
An exception to sequential chaining of CCWs occurs when the I/O device presents
status modifier with device end. When
no unusual conditions have been detected
and command chaining is specified or
when command retry has been previously
signaled and an immediate retry could
not be performed, the combination of
status modifier and device end causes
the channel to alter the sequential
execution of CCWs. If command chaining
was specified, status modifier and
device end cause the channel to chain to
the CCW whose storage address is 16
higher than that of the CCW that speci­
fied chaining. If command retry was
previously signaled and immediate retry
could not be performed, the status caus­
es the channel to command-chain to the CCW whose storage address is 8 higher
than that of the CCW for which retry was
initially signaled.
When both command and data chaining are
used, the first CCW associated with the
operation specifies the operation to be
executed, and the last CCW indicates
whether another operation follows. Programming Note Command chaining makes it possible for
the program to initiate transfer of
multiple blocks by means of a single
START 1/0 or START I/O FAST RELEASE. It
also permits a subchannel to be set up
for the execution of auxiliary
functions, such as positioning the
disk-access mechanism, and for data­
transfer operations without interference
by the program at the end of each opera­
tion. Command chaining, in conjunction
with the status-modifier condition,
permits the channel to modify the normal
sequence of operations in response to
signals provided by the I/O device. SKIPPING Skipping causes the suppression of stor­
age references during an I/O operation.
It is defined only for read, read back­
ward, and sense operations and is
controlled by the skip flag, which can
be specified individually for each CCW. When the skip flag is one, skipping
occurs; when zero, normal operation Chapter 13. Input/Output Operations 13-43
takes place. The setting of the skip
flag is ignored in all other operations. Skipping affects only the handling of
information by the channel. The opera­
tion at the I/O device proceeds
normally, and information is transferred to the channel. The channel keeps
updating the count but does not place
the information in storage. Chaining is
not precluded by skipping. In the case
of data chaining, normal operation is
resumed if the skip flag in the new CCW is zero.
When the skip flag is set to one, the
data address in the CCW is not checked.
Programming Note
Skipping, when combined with data chain­
ing, permits the program to place in
storage selected portions of a block
from an I/O device. PROGRAM-CONTROLLED INTERRUPTION
The program-controlled-interruption (PCI) function permits the program to
cause an I/O interruption during the
execution of an I/O operation. The
function is controlled by the PCI flag
in the CCW. The flag can be on either
in the first CCW specified by START I/O or START I/O FAST RELEASE or in a CCW fetched during chaining or command
retry. Neither the PCI flag nor the
associated interruption affects the
execution of the current operation.
Whenever the PCI flag in the CCW is one,
an interruption condition is generated
in the channel. When the first CCW associated with an operation contains
the PCI flag, either initially or upon
command chaining, the interruption may
occur as early as immediately upon the
initiation of the operation. The PCI flag in a CCW fetched on data chaining
causes the interruption to occur after
all data designated by the preceding CCW has been transferred. The time of the
interruption, however, depends on the
model and the current activity in the
system and may be delayed even if I/O interruptions are allowed. No predict­
able relationship exists between the
time the interruption due to the PCI flag occurs and the progress of data
transfer to or from the area designated
by the CCW, but the fields within the CSW pertain to the same instant of time.
If chaining occurs before the inter­
ruption due to the PCI flag has taken
place, the PCI interruption condition is
carried over to the new CCW. This
13-44 System/370 Principles of Operation carryover occurs both on data and
command chaining and, in either case,
the interruption condition is propagated
through the transfer-in-channel command.
The interruption conditions due to the PCI flags are not stacked; that is, if
another CCW is fetched with a PCI flag
before the interruption due to the PCI flag of the previous CCW has occurred,
only one interruption takes place.
A CSW containing the PCI bit set to one
may be stored by an interruption while
the operation is still proceeding, while
channel-program execution is suspended,
or by an interruption, TEST I/O, or CLEAR I/O upon the termination of the
operation. A CSW cannot be stored by
TEST I/O while the subchannel is in the
working state.
When the CSW is stored by an inter­
ruption before the operation or chain of
operations has been concluded, the CCW address is 8 greater than the address of
the CCW that contained the last recog­
nized PCI flag or 8 greater than the
address of a CCW which has subsequently
become current, and the count is unpre­
dictable. All unit-status bits in the CSW are zero. If the channel has
detected any unusual situations, such as
channel-data check, program check, or
protection check by the time the inter­
ruption occurs, the corresponding
channel-status bit is one, although the
status in the subchannel is not reset
and is indicated again upon the termi­
nation of the operation.
A unit-status bit set to one in the CSW indicates that the operation or chain of
operations has been concluded. The CSW in this case has its regular format with
the PCI bit set to one.
However, when the interruption due to
the PCI flag is delayed until the opera­
tion at the subchannel is concluded, two
interruptions from the subchannel may
still take place. The first inter­
ruption indicates and clears the
interruption condition due to the PCI flag, and the second provides the CSW associated with the ending status.
Whether one or two interruptions occur
depends on the model and on whether the
interruption condition due to the PCI flag has been assigned the highest
priority for interruption at the time of
conclusion. TEST I/O or CLEAR I/O addressed to the device associated with
an interruption condition in the
subchannel clears the interruption
condition due to the PCI flag, as well
as the one associated with the conclu­
sion.
The setting of
in every CCW transfer in
ignored. The
during initial
the PCI flag is inspected
except those specifying
channel, where it is PCI flag is also ignored
program loading.
Previous Page Next Page