STD field is placed in both the PSTD and SSTD, bits 0-31 of control registers 1
and 7, respectively. The contents of
the entire STD field are placed in the
appropriate control registers without
being inspected for validity.
Space-Switch-Event Control (X): Bit 31
of the segment-table designation is the
space-switch-event-control bit. When,
in PC-ss or PT-ss, this bit is one in
control register 1 either before or
after the execution of the PC-ss or
PT-ss, a program interruption for a space-switch event occurs after the
execution of the instruction is completed. When, in LOAD ADDRESS SPACE
PARAMETERS, this bit is one during
primary ASN translation, this fact is indicated by the condition code.
Linkage-Table Designation (LTD): Bits
96 and 104-127 are used as a result of
primary ASN translation. The linkage­
table-designation field contains the
subsystem-linkage-control bit (V) (bit
96), the linkage-table origin (LTD)
(bits 104-120), and the linkage-table
length (LTL) (bits 121-127). The
contents of the LTD field are placed in
control register 5 as a result of prima­
ry ASN translation.
Bits 1-7, 30, 31, 60-63, and 97-103 of
the AST entry must be zeros; otherwise,
an ASH-translation-specification excep­
tion is recognized as part of the
execution of the instruction using that
entry for ASN translation.
Programming Note
The unused portion of the STD field,
bits 90-94 of the AST entry, which
corresponds to bits 26-30 of the PSTD
and SSTD, should be set to zeros. These
bits are reserved for future expansion,
and programs which place nonzero values
in these bit positions may not operate
compatibly on future machines.
ASN-TRANSLATION PROCESS
This section describes the ASN­
translation process as it is performed
during the execution of PROGRAM CALL
with space switching, PROGRAM TRANSFER
with space switching, and SET SECOHDARY ASH with space switching. ASH trans­
lation for LOAD ADDRESS SPACE PARAMETERS
is the same, except that AFX-translation
and ASX-translation exceptions do not
occur; such situations are instead indi­
cated by the condition code.
Translation of an ASN is performed by
means of two tables, an ASN first table and an ASN second table, both of which
reside in main storage.
The ASH first index is used to select an entry from the ASN first table. This
entry designates the ASN second table to
be used.
The ASH second index is used to select
an entry from the ASN second table.
This entry contains the address-space­
control parameters.
If the I bit is one in either the ASN­
first-table entry or ASN-second-table
entry, the entry is invalid, and the
ASN-translation process cannot be
completed. An AFX-translation exception
or ASX-translation exception is recog­
nized. Whenever access to main storage is made
during the ASN translation process for the purpose of fetching an entry from an
ASN first table or ASN second table,
key-controlled protection does not
apply.
The ASN translation process is shown in
the figure "ASN Translation."
Chapter 3. Storage 3-15

ASH CR14 (x4) (x16) ASH First Table R
I ASTO o
(x16) ASH Second Table
R
I I 0 I ATO 1
0
1 AX I R: Address is real ASH Translation
ASH-First-Table Lookup
The AFX portion of the ASH, in conjunc­
tion with the ASH-first-table origin, is
used to select an entry from the ASH second table. The 24-bit real address of the ASH­ first-table entry is obtained by append­
ing 12 zeros on the right to the AFT
origin contained in bit positions 20-31
of control register 14 and adding the
AFX with two rightmost and 12 leftmost
zeros appended. This addition cannot
cause a carry into bit position 7. With extended real addressing, this 24-bit
real address is extended on the left
with zeros.
All four bytes of the ASH-first-table entry appear to be fetched concurrently
as observed by other CPUs. The fetch
access is not subject to protection. When the storage address which is gener­ ated for fetching the ASH-first-table entry designates a location which is not
available in the configuration, an
3-16 System/370 Principles of Operation ATL 101 STD I V I 0 I L TO ILTL addressing exception is recognized, and
the operation is suppressed.
Bit 0 of the four-byte AFT entry speci­
fies whether the corresponding AST is
available. If this bit is one, an AFX­
translation exception is recognized. If
bit positions 1-7 and 28-31 of the AFT
entry do not contain zeros, an ASN­ translation-specification exception is
recognized. When no exceptions are
recognized, the entry fetched from the AFT is used to access the AST. ASH-Second-Table Lookup The ASX portion of the ASH, in conjunc­ tion with the ASH-second-table orlgln
contained in the ASH-first-table entry,
is used to select an entry from the ASH second table. The 24-bit real address
second-table entry is
appending four zeros on
of the obtained the right ASH­ by
to