bits 8-27 of the ASN-first-table entry
and adding the ASX portion with four
rightmost and 14 leftmost zeros
appended. A carry, if any, into bit
position 7 is ignored. With extended
real addressing, this 24-bit real
address is extended on the left with
zeros; thus, the ASN-second table can
wrap from 224 -1 to zero.
The 16 bytes of the ASN-second-table
entry appear to be fetched word­
concurrent as observed by other CPUs, with the leftmost word fetched first.
The order in which the remaining three
words are fetched is unpredictable. The
fetch access is not subject to
protection. When the storage address
which is generated for fetching the
ASN-second-table entry designates a
location which is not available in the
configuration, an addressing exception
is recognized, and the operation is suppressed.
Bit 0 of the 16-byte ASN-second-table
entry specifies whether the address
space is accessible. If this bit is one, an ASX-translation exception is
recognized. If bit positions 1-7, 30, 31, 60-63, and 97-103 of the ASN­
second-table entry do not contain zeros,
an ASN-translation-specification excep­
tion is recognized.
Recognition of Exceptions during ASN
Translation
The exceptions which can be encountered
during the ASH-translation process are
collectively referred to as ASH­ translation exceptions. A list of these
exceptions and their priorities is given in Chapter 6, "Interruptions." ASH AUTHORIZATION ASH authorization is the process of
testing whether the program associated
with the current authorization index is permitted to establish a particular
address space. The ASH authorization is performed as part of PROGRAM TRANSFER
with space switching (PT-ss) and SET SECONDARY ASH with space switching
(SSAR-ss) and may be performed as part
of LOAD ADDRESS SPACE PARAMETERS. ASN
authorization is performed after the ASH-translation process for these
instructions.
When performed as part of PT-ss, the ASH authorization tests whether the ASH can
be established as the primary ASH and is called primary-ASH authorization. When
performed as part of LOAD ADDRESS SPACE PARAMETERS or SSAR-ss, the ASH authori­ zation tests whether the ASH can be
established as the secondary ASN and is
called secondary-ASN authorization.
The ASN authorization is performed by
means of an authority table in real
storage which is designated by the
authority-table-origin and authority­
table-length fields in the ASN-second­
table entry. ASH-AUTHORIZATION COHTROLS ASN authorization uses the authority­
table origin and the authority-table
length from the ASH-second-table entry,
together with an authorization index. Control Register For PT-ss and SSAR-ss, the current
contents of control register 4 include
the authorization index. For LOAD ADDRESS SPACE PARAMETERS, the value
which will become the new contents of
control register 4;s used. The regis­
ter has the following format:
AX a 15
Authorization Index (AX): Bits 0-15 of
control register 4 are used as an index
to locate the authority bits in the
authority table.
ASN-Second-Table Entry
The ASN-second-table entry which is
fetched as part of the ASH translation
process contains information which is
used to designate the authority table.
An entry in the ASN second table has the
following format: 100000001 ATO 1
00 I o 1 8 31
ATl 1
0000 I 32 48 60 64
Authority-Table Origin (ATO): Bits
8-29, with two zeros appended on the
right, are used to form a 24-bit real
address that designates the beginning of
the authority table. With extended real
addressing, the authority-table origin Chapter 3. Storage 3-17

is still a 24-bit real address and is
extended on the left with zeros.
Authority-Table Length (AIl): Bits
48-59 specify the length of the authori­
ty table in units of four bytes, thus
making the authority table variable in
multiples of 16 entries. The length of
the authority table, in units of four
bytes, is equal to one more than the ATL
value. The contents of the length field are used to establish whether the entry
designated by the authorization index
falls within the authority table.
Authority-Table Entries
The authority table consists of entries
of two bits each; accordingly, each byte
of the authority table contains four
entries in the following format:
o 7
The fields are allocated as follows: Primary Authority (E): The left bit of
an authority-table entry controls wheth­
er the program with the authorization
index corresponding to the entry is
permitted to establish the address space
as a primary address space. If the P bit is one, the access is permitted. If
the P bit is zero, the access is not
permitted.
Secondary Authority of an authority-table
The right bit
entry controls
3-18 System/370 Principles of Operation whether the program with the correspond­
ing authorization index is permitted to
establish the address space as a second­ ary address space. If the S bit is one,
the access is permitted. If the S bit
is zero, the access is not permitted. ASN-AUTHORIZATION PROCESS This section describes the ASN­
authorization process as it is performed
during the execution of PROGRAM TRANSFER
with space switching and SET SECONDARY ASN with space switching. For these two
instructions, the ASN-authorization
process is performed by using the
authorization index currently in control
register 4. Secondary authorization for LOAD ADDRESS SPACE PARAMETERS is the
same, except that the value which will
become the new contents of control
register 4 is used for the authorization
index, and a secondary-authority excep­
tion does not occur. Instead, such a situation is indicated by the condition code.
The ASN-authorization process is
performed by using the authorization
index, in conjunction with the
authority-table origin and length from
the AST entry, to select an authority­
table entry. The entry is fetched, and
either the primary-or secondary­
authority bit is examined, depending on
whether the primary-or secondary-ASH­
authorization process is being
performed. The ASN-authorization proc­
ess is shown in the figure "ASH Authorization."