branch-and-save facility, the BRANCH AND
SAVE (BAS or BASR) instructions may be
used for the same purpose. Both save
the address of the next instruction as
link information in a general register
and then cause execution to continue
from a different instruction sequence at the branch address specified by this instruction. They differ in that BRANCH
AND LINK places additional information
(the instruction-length code, condition
code, and program mask) in the leftmost
byte of the link information, whereas
BRANCH AND SAVE places zeros in that byte.
BRANCH AND SAVE, when available, is
recommended for use in place of BRANCH
AND LINK in programs that are intended
to be executed on System/370 models
equipped with the extended-architecture (370-XA) mode. When such a model is
operating in the 370-XA mode, the infor­
mation placed by BRANCH AND LINK in the leftmost byte of the linkage register
while 24-bit addressing is in effect may
lead to problems if the same program may
be used with 31-bit addressing; BRANCH
AND SAVE sets the leftmost byte to zero
with 24-bit addressing, which is compat­
ible with 31-bit addressing. (For more
information on 31-bit addressing and on
subroutine linkage methods for the 370-XA mode, see the IBM System/370 Extended Architecture Principles of
Operation, SA22-7085.) The following example compares the oper­
ation of these instructions and of the
unconditional-branch instruction BRANCH ON CONDITION (BC or BCR with a mask of
15). Assume that each instruction in
turn ;s located at the current instruc­
tion address, ready to be executed next.
Assume also that general register 5 is
to receive the linkage information, and
that general register 6 contains the branch address.
The format of the BALR instruction is:
Machine Format Op Code 05 5 6
Assembler Format
BALR 5,6
The BASR instruction has the same
format, but the op code is OD. For comparison with the RR-format
instructions, the results of two
RX-format instructions are also shown.
The format of the BAL instruction is:
Machine Format Op Code
45 5 o 6 0001 Assembler Format
BAL 5,0(0,6) The BAS instruction has the same format,
but the op code is 4D.
The BCR instruction specifies only one
register:
Machine Format Op Code 07 F 6
Assembler Format
BCR 15,6
Assume that:
Register 5 contains BB BB BB BB.
Register 6 contains 82 46 8A CEo
PSW bits 32-63 contain 00 00 10 D6.
Condition code is 01{2}. Program mask is 1100{2}. The effect of executing each instruction
in turn is as follows:
Instruction Register 2 PSW (32-63)
Before BB BB BB BB 00 00 10 D6
BCR 15,6 BB BB BB BB 00 46 8A CE
BAL 5,0(0,6) 9C 00 10 DA 00 46 8A CE
BAS 5,0(0,6) 00 00 10 DA 00 46 8A CE
BALR 5,6 5C 00 10 D8 00 46 8A CE
BASR 5,6 00 00 10 D8 00 46 8A CE
Note that a value of zero in the R2 field of any of the RR-format
instructions indicates that the branch­
ing function is not to be performed; it
does not refer to register O. Thus, the
instruction BALR 8,0 may be used to
preserve the current condition code in
bits 2 and 3 of register 8 for future
inspection. Register 0 can be desig­
nated by the Rt field, however. In the
RX-format branch instructions, branching
occurs independent of whether there is a
value of zero in the B2 field or X 2 Appendix A. Number Representation and Instruction-Use Examples A-9

field of the instruction. However, when
the field is zero, instead of using the
contents of general register 0, a value
of zero is used for that component of
address generation. Other BALR and BASR Examples
The BAlR or BASR instruction with the R2
field set to zero may be used to load a register for use as a base register.
For example, in the assembler language,
the two statements:
BALR USING or
BASR USING 15,0 *,15 indicate that the address of the next
sequential instruction following the
BALR or BASR instruction will be placed
in register 15, and that the assembler
may use register 15 as a base register
until otherwise instructed. (The USING statement is an "assembler instruction"
and is thus not a part of the object
program. ) BRANCH ON CONDITION (BC, BCR) The BRANCH ON CONDITION tests the condition code to see whether
a branch should or should not occur.
The branch occurs only if the current
condition code corresponds to a one bit
in a mask specified by the instruction. Condition Code -0- 1
2
3
Instruction
(Mask) Bit
8-
9 10 11
Mask
Value
-8-
4
2
1
For example, assume that an ADD (A or
AR) operation has been performed and
that a branch to address 6050 is desired
if the sum is zero or less (condition
code is 0 or 1). Also assume:
Register 10 contains 00 00 50 00. Register 11 contains 00 00 10 00. The RX form of the instruction performs
the required test (and branch if neces­
sary) when written as: A-I0 System/370 Principles of Operation Machine Format Op Code M t
47 C B
A 1 050
1 Assembler Format Op Code M
t ,D
2
(X 2 ,B
2
) BC 12,X'50'(11,10) A mask of 12{10} means that there are
ones in instruction bits 8 and 9 and
zeros in bits 10 and 11, so that branch­
ing takes place when the condition code
is either 0 or 1.
A mask of 15 would indicate a branch on
any condition (an unconditional branch).
A mask of zero would indicate that no
branch is to occur (a no-operation).
(See also the section on "Linkage
Instructions (BAL, BALR, BAS, BASR)" for
an example of the BCR instruction.) BRANCH ON COUNT (BCT, BCTR) The BRANCH ON COUNT instruction is often
used to execute a program loop for a
specified number of times. For example,
assume that the following represents
some lines of coding in an assembler­
language program:
.
LUPE AR 8,1
. BACK BCT 6,LUPE
where register 6 contains 00 00 00 03 and the address of LUPE is 6826. Assume
that, in order to address this location,
register 10 is used as a base register
and contains 00 00 68 00. The format of the BCT instruction is: