Machine Format Op Code R, 7E 6 o o 0001 Assembler Format AU 6,0(0,13) is executed, the two numbers are added
as follows: FPR6 Shifted number from
storage
Intermediate sum
1 Guard digit
Fraction GOl
-43 08 21 00 +43 00 12 34 5
-43 08 OE CB B The guard digit participates in the
addition but is discarded. The unnor­
mali zed sum replaces the left half of FPR6. Condition code 1 is set because
the result is less than zero.
The truncated result in FPR6 (C3 08 OE CB 00 00 00 00) shows a loss of a
significant digit when compared to the
result of short-precision normalized
addition. COMPARE (CO, CDR, CE, CER) Assume that FPR4 contains 43 00 00 00 00 00 00 00 (zero), and FPR6 contains 35 12
34 56 78 9A BC DE (a positive number).
The contents of the two registers are to be compared using a long-precision COMPARE instruction.
Machine Format Op Code R, 29 4 6
Assembler Format CDR 4,6
The number with the smaller character­
istic, which is in register FPR6, is
right-shifted 43 -35 hex (67 -53 deci­
mal) or 14 digit positions, so that the
two characteristics agree. The shifted
number is 43 00 00 00 00 00 00 00, with
a guard digit of one. Therefore, when
the two numbers are compared, condition
code 1 is set, indicating that operand 1
in FPR4 is less than operand 2 in FPR6. If the example is changed to a second
operand with a characteristic of 34
instead of 35, so that FPR6 contains 34
12 34 56 78 9A BC DE, the operand is
right-shifted 15 positions, leaving all
fraction digits and the guard digit as
zeros. Condition code 0 is set, indi­
cating equality. This example shows
that two floating-point numbers with
different characteristics or fractions
may compare equal if the numbers are
unnormalized or zero.
As another example of comparing unnor­
mali zed floating-point numbers, 41 00 12
34 56 78 9A BC compares equal to all
numbers of the form 3F 12 34 56 78 9A BC OX (X represents any hexadecimal digit). When the COMPARE instruction is
executed, the two rightmost digits are
shifted right two places, the 0 becomes
the guard digit, and the X does not
participate in the comparison.
However, when two normalized floating-
point numbers are compared, the relationship between numbers that
compare equal is unique: each digit in
one number must be the same as the
corresponding digit in the other number.
DIVIDE (DO, OOR, DE, OER)
Assume that the first operand (the divi­
dend) is in FPR2 and the second operand
(the divisor) in FPRO. If the operands
are in the short-precision format, the
resulting quotient is returned to FPR2 by the instruction:
Machine Format Op Code R, 3D 2 o
Assembler Format
DER 2,0 Several examples of short-precision
floating-point division, with the divi­
dend in FPR2 and the divisor in FPRO, are shown below. For case A, the
result, which replaces the dividend, is
obtained in the following steps.
Appendix A. Number Representation and Instruction-Use Examples A-37

7.2522F .123400 1.821000 7F6COO 2A400 0 24680 0 5D80 00 5B04 00 27C 000 246 800 35 8000 24 6800 11 18000 11 10COO 7400 FPR2 Before FPRO FPR2 After Case (Dividend) (D i v i so r) A -43 082100 +43 001234 -42 72522F
B +42 101010 +45 111111 +3D FOFOFO C +48 30000F +41 400000 +47 COO03C D +48 30000F +41 200000 +48 180007 E +48 180007 +41 200000 +47 COO038 Case C shows a number being divided by 4.0. Case D divides the same number by 2.0, and case E divides the result of
case D again by 2.0. The results of
cases C and E differ in the rightmost
hexadecimal digit position, which illus­
trates an effect of result truncation.
HALVE (HDR, HER)
HALVE produces the same result as
floating-point DIVIDE with a divisor of 2.0. Assume FPR2 contains the long­
precision number +48 30 00 00 00 00 00 OF. The following HALVE instruction
produces the result +48 18 00 00 00 00 00 07 in FPR2: Machine Format Op Code 24 2 2
Assembler Format
HDR 2,2
A-38 System/370 Principles of Operation MULTIPLY (MO, MDR, ME, MER, MXO, MXOR, MXR)
For this example, the following 10ng­ precision operands are in FPRO and FPR2: FPRO: -33 606060 60606060 FPR2: -5A 200000 20000020 A long-precision product is generated by
the instruction:
Machine Format Op Code 2C o 2
Assembler Format
MDR 0,2 If the operands were not already normal­ ized, the instruction would first
normalize them. It then generates an
intermediate result consisting of the
full 28-digit hexadecimal product frac­
tion obtained by multiplying the
14-digit hexadecimal operand fractions,
together with the appropriate sign and a
characteristic that is the sum of the
operand characteristics less 64 (40 hex) :
The fraction multiplication is performed
as follows: .60606060606060 .20000020000020 COCOCOCOCOCOCOO COCOCOCOCOCOCO COCOCOCOCOCOCO .OCOCOC181818241818180COCOCOO Attaching the sign and characteristic to
the fraction gives: +40 aCOCDC 18181824 1818180C OCOCOO Because this intermediate product has a
leading zero, it is then normalized.
The truncated final result placed in FPRO is:
+4C COCOC1 81818241 FLOATING-POINT-NUMBER CONVERSION The following examples illustrate one
method of converting between binary
fixed-point numbers (32-bit signed bina­
ry integers) and normalized floating­
point numbers. Conversion must provide
for the different representations used