with negative numbers: the two's­
complement form for signed binary
integers, and the signed-absolute-value
form for the fractions of floating-point
numbers. Fixed Point to Floating Point
The method used here inverts the left­
most bit of the 32-bit signed binary
integer, which is equivalent to adding 2
31 to the number and considering the
result to be positive. This changes the
number from a signed integer in the
range 2
31
- 1 through -2
31
to an
unsigned integer in the range 2
32 - 1
through o. After conversion to the long
floating-point format, the value 2
31
is
subtracted again.
Assume that general register 9 (GR9)
contains the integer -59 in two's­
complement form:
GR9: FF FF FF C5 Further, assume two eight-byte fields in
storage: TEMP, for use as temporary
storage, and TW03I, which contains the
floating-point constant 2
31
in the
following format: TW03I: 4E 00 00 00 80 00 00 00 This is an unnormalized long floating­
point number with the characteristic 4E,
which corresponds to a radix point (hex­
adecimal point) to the right of the
number.
The following instruction sequence
performs the conversion:
Result
X 9,TW03I+4 GR9:
7FFF FFC5
ST 9,TEMP+4 TEMP:
xxxx xxxx 7FFF FFC5 MVC TEMP(4),TW03I TEMP: 4EOO 0000 7FFF FFC5 LO 2,TEMP FPR2: 4EOO 0000 7FFF FFC5 SO 2,TW03I FPR2: C23B 0000 0000 0000 The EXCLUSIVE OR (X) instruction inverts
the leftmost bit in general register 9,
using the right half of the constant as
the source for a leftmost one bit. The
next two instructions assemble the modi­
fied number in an unnormalized long
floating-point format, using the left
half of the constant as the plus sign,
the characteristic, and the leading
zeros of the fraction. LOAD (LD) places
the number unchanged in floating-point
register 2. The SUBTRACT NORMALIZED (SO) instruction performs the final two
steps by subtracting 2
31 in floating­
point form and normalizing the result.
Floating Point to Fixed Point
The procedure described here consists
basically in reversing the steps of the
previous procedure. Two additional
considerations must be taken into
account. First: the floating-point
number may not be an exact integer.
Truncating the excess hexadecimal digits
on the right requires shifting the
number one digit position farther to the
right than desired for the final result,
so that the units digit occupies the
position of the guard digit. Second:
the floating-point number may have to be
tested as to whether it is outside the
range of numbers representable as a
32-bit signed binary integer.
Assume that floating-point register 6
contains the number 59.25{10} = 3B.4{16}
in normalized form:
FPR6: 42 3B 40 00 00 00 00 00 Further, assume three eight-byte fields
in storage: TEMP, for use as temporary
storage, and the constants 2
32 (TW032) and 2
31 (TW03IR) in the following
formats: TW032: TW03IR: 4E 00 00.01 00 00 00 00 4F 00 00 00 08 00 00 00 The constant TW031R is shifted right one
more position than the constant TW031 of
the previous example, so as to force the
units digit into the guard-digit posi­
tion.
The following instruction sequence
performs the integer truncation, range
tests, and conversion to a signed binary
integer in general register 8 (GR8):
Result SO 6,TW03IR FPR6: C87F FFFF C500 0000 BC II,OVERFLOW Branch to overflow
routine if result
is greater than or
equal to zero
AW 6,TW032 FPR6: 4EOO 0000 8000 003B BC 4,OVERFLOW Branch to overflow
routine if result
is less than zero STD 6,TEMP TEMP: 4EOO 0000 8000 003B XI TEMP+4,X'80' TEMP: 4EOO 0000 0000 003B L 8,TEMP+4 GR8: 0000 003B Appendix A. Number Representation and Instruction-Use Examples A-39

The SUBTRACT NORMALIZED (SD) instruction
shifts the fraction of the number to the
right until it lines up with TW03IR, which causes the fraction digit 4 to
fall to the right of the guard digit and
be lost; the result of subtracting 2
31 from the remaining digits is renormal­
ized. The result should be less than
zero; if not, the original number was
too large in the positive direction.
The first BRANCH ON CONDITION (BC) performs this test.
The ADD UNNORMALIZED (AW) instruction
adds 232: 2
31
to correct for the previ­
ous subtraction and another 2
31
to
change to an all-positive range. The
second BC tests for a result less than
zero, showing that the original number
was too large in the negative direction.
The unnormalized result is placed in
temporary storage by the STORE (STD)
instruction. There the leftmost bit of
the binary integer is inverted by the EXCLUSIVE OR (XI) instruction to
subtract 2
31 and thus convert the
unsigned number to the signed format.
The final result is loaded into GR8. MULTIPROGRAMMING AND MULTIPROCESSING EXAMPLES -
When two or more programs sharing common
storage locations are being executed
concurrently in a multiprogramming or
multiprocessing environment, one program
may, for example, set a flag bit in the
common-storage area for testing by
another program. It should be noted
that the instructions AND (NI or NC), EXCLUSIVE OR (XI or XC), and OR (01 or OC) could be used to set flag bits in a multiprogramming environment; but the
same instructions may cause program
logic errors in a multiprocessing
configuration where two or more CPUs can
fetch, modify, and store data in the
same storage locations simultaneously.
EXAMPLE OF A PROGRAM FAILURE USING OR IMMEDIATE
Assume that two independent programs try
to set different bits to one in a common
byte in storage. The following example
shows how the use of the instruction OR immediate (01) can fail to accomplish
this, if the programs are executed
simultaneously on two different CPUs. One of the possible error situations is depicted. A-40 System/370 Principles of Operation Execution of
instruction 01 FLAGS,X'Ol' on CPU A
Fetch FLAGS X'OO' OR X'OI' into X'OO' Store X'OI' into FLAGS
Execution of
instruction FLAGS 01 FLAGS,X'SO' on CPU B X'OO' Fetch
FLAGS X'OO' X'OO' X'OO' OR X'80' into X'OO' X'OO' X'80' Store X'80' into FLAGS X'OI' FLAGS should have value of X'SI' following both updates.
The problem shown here is that the value
stored by the 01 instruction executed on CPU A overlays the value that was stored
by CPU B. The X'80' flag bit was erro­
neously turned off, and the data is now
invalid.
The COMPARE AND SWAP instruction has
been provided to overcome this and simi­
lar problems. CONDITIONAL SWAPPING INSTRUCTIONS (CS, CDS) The COMPARE AND SWAP (CS) and COMPARE DOUBLE AND SWAP (CDS) instructions can
be used in multiprogramming or multi­
processing environments to serialize
access to counters, flags, control
words, and other common storage areas.
The following examples of the use of the COMPARE AND SWAP and COMPARE DOUBLE AND
SWAP instructions illustrate the appli­
cations for which the instructions are
intended. It is important to note that
these are examples of functions that can
be performed by programs while the CPU is enabled for interruption (multipro­
gramming) or by programs that are being
executed in a multiprocessing configura­
tion. That is, the routine allows a
program to modify the contents of a
storage location while the CPU is
enabled, even though the routine may be
interrupted by another program on the
same CPU that will update the location,
and even though the possibility exists
that another CPU may simultaneously
update the same location.
The COMPARE AND SWAP instruction first
checks the value of a storage location
and then modifies it only if the value
is what the program expects; normally
this would be a previously fetched
value. If the value in storage is not
what the program expects, then the