location is not modified; instead, the
current value of the location is loaded
into a general register, in preparation for the program to loop back and try
again. During the execution of COMPARE AND SWAP, no other CPU can perform a
store access or interlocked-update
access at the specified location.
Setting g Single Bit
The following instruction sequence shows
how the COMPARE AND SWAP instruction can
be used to set a single bit in storage
to one. Assume that the first byte of a
word in storage called "WORD" contains
eight flag bits.
LA 6,X'80' SLL 6,24
L RETRY LR OR CS BC 7,WORD 8,7
8,6
7,8,WORD 4,RETRY Put bit to be ORed into GR6
Shift left 24 places
to align the byte
to be ORed with
the location of
the flag bits
within WORD Fetch current flag
values
load flags into GR8 Set bit to one Store new flags if
current flags un­
changed, or re­
fetch current
flag values if
changed
If new flags are not
stored, try again
The format of the COMPARE AND SWAP instruction is: Machine Format Op Code BA 7
Assembler Format CS 7,8,WORD
The COMPARE AND SWAP instruction
compares the first operand (general
register 7 containing the current flag
values) to the second operand in storage (WORD) while no CPU other than the one
executing the COMPARE AND SWAP instruc­
tion is permitted to perform a store
access or interlocked-update access at
the specified storage location.
If the comparison is successful, indi­
cating that the flag bits have not been
changed since they were fetched, the
modified copy in general register 8 is
stored into WORD. If the flags have
been changed, the compare will not be
successful, and their new values are
loaded into general register 7.
The conditional branch (BC) instruction
tests the condition code and reexecutes
the flag-modifying instructions if the COMPARE AND SWAP instruction indicated
an unsuccessful comparison (condition
code 1). When the COMPARE AND SWAP instruction is successful (condition
code 0), the flags contain valid data,
and the program exits from the loop.
The branch to RETRY will be taken only if some other program modifies the
contents of WORD. This type of a loop
differs from the typical "bit-spin"
loop. In a bit-spin loop, the program
continues to loop until the bit changes.
In this example, the program continues
to loop only if the value does change
during each iteration. If a number of CPUs simultaneously attempt to modify a
single location by using the sample
instruction sequence, one CPU will fall
through on the first try, another will loop once, and so on until all CPUs have
succeeded.
Updating Counters In this example, a 32-bit counter is
updated by a program using the COMPARE AND SWAP instruction to ensure that the
counter will be correctly updated. The
original value of the counter is
obtained by loading the word containing
the counter into general register 7.
This value is moved into general regis­
ter 8 to provide a modifiable copy, and
general register 6 (containing an incre­
ment to the counter) is added to the
modifiable copy to provide the updated
counter value. The COMPARE AND SWAP instruction is used to ensure valid
storing of the counter.
The program updating the counter checks
the result by examining the condition
code. The condition code 0 indicates a
successful update, and the program can
proceed. If the counter had been changed between the time that the
program loaded its original value and
the time that it executed the COMPARE AND SWAP instruction, the execution
would have loaded the new counter value
into general register 7 and set the
condition code to 1, indicating an
unsuccessful update. The program must
then repeat the update sequence until
the execution of the COMPARE AND SWAP instruction results in a successful
update.
The following instruction
performs the above procedure:
sequence
Appendix A. Number Representation and Instruction-Use Examples A-41

LA 6,1 Put increment (1) into
GR6
L 7,CNTR Put original counter
value into GR7 LOOP LR 8,7 Set up copy in GR8 to
modify
AR 8,6 Increment copy CS 7,8,CNTR Update counter in
storage BC 4,LOOP If original value had
changed, update new
value
The following shows two CPUs, A and B,
executing this instruction sequence
simultaneously: both CPUs attempt to
add one to CNTR. CPU A CPU B Comments GR7 GR8 CNTR GR7 GR8 16
16 16 CPU A loads GR7
and GR8 from CNTR 16 16 CPU B loads GR7
and GR8 from CNTR 17 CPU B adds one
to GR8
17 CPU A adds one
to GR8
17 CPU A executes CSi successful
match, store
17 CPU B executes CS; no match,
GR7 changed to CNTR value
18 CPU B loads GR8
from GR7, adds
one to GR8
18 CPU B executes CSi successful
match, store BYPASSING POST AND WAIT BYPASS POST Routine
The following routine allows the SVC "POST" as used in OS/VS to be bypassed
whenever the corresponding WAIT has not
yet been executed, provided that the
supervisor WAIT and POST routines use COMPARE AND SWAP to manipulate event
control blocks (ECBs). GRO contains the POST code.
GR1 contains the address of the ECB. GR5 contains 40 00 00 00{16} A-42 System/370 Principles of Operation HSPOST OR 0,5 Set bit 1 of
GR1 to one
L 3,0(1) GR3 = contents
of ECB LTR 3,3 ECB marked 'waiting'! BC 4,PSVC Yes, execute
post SVC CS 3,0,0(1) No, store post
code BC 8,EXITHP Continue PSVC POST (1),(0) ECB address is EXITHP [Any instruction]
in GR1, post
code in GRO The following routine may be used in
place of the previous HSPOST routine if
it is assumed that bit 1 of the contents
of GRO is already set to one and if the ECB is assumed to contain zeros when it
is not marked "WAITING." HSPOST SR 3,3 CS 3,0,0(1) BC 8,EXITHP POST (1),(0) EXITHP [Any instruction] BYPASS WAIT Routine
A BYPASS WAIT function, corresponding to
the BYPASS POST, does not use the CS instruction, but the FIFO LOCK/UNLOCK routines which follow assume its use.
HSWAIT TM BC O(1),X'40' 1,EXITHW If bit 1 is one,
then ECB is al­
ready posted;
branch to exit
WAIT ECB=(l) EXITHW [Any instruction] LOCK/UNLOCK When a common storage area larger than a
doubleword is to be updated, it is usually necessary to provide special
interlocks to ensure that a single
program at a time updates the common
area. Such an area is called a serially
reusable resource (SRR).
In general, updating a list, or even
scanning a list, cannot be safely accom­
plished without first "freezing" the
list. However, the COMPARE AND SWAP and COMPARE DOUBLE AND SWAP instructions can
be used in certain restricted situations
to perform queuing and list
manipUlation. Of prime importance is
the capability to perform the
lock/unlock functions and to provide
sufficient queuing to resolve