This appendix lists the condition-code
setting for instructions in the System/370 architecture which set the
condition code. In addition to those
instructions listed which set the condi­
tion code, the condition code may be
changed by DIAGNOSE and the target of EXECUTE. The condition code is loaded
by LOAD PSW, by SET PROGRAM MASK, and by
an interruption. The condition code is
set to zero by initial CPU reset and is
loaded by the successful conclusion of
the initial-program-loading sequence.
Instruction
ADD, ADD HALFWORD ADD DECIMAL
ADD LOGICAL ADD NORMALIZED
ADD UNNORMALIZED AND
CLEAR CHANNEL
CLEAR I/O COMPARE (gen, fl pt) COMPARE HALFWORD COMPARE AND SWAP COMPARE DECIMAL COMPARE DOUBLE AND SWAP COMPARE LOGICAL COMPARE LOGICAL CHARACTERS UNDER MASK COMPARE LOGICAL LONG CONNECT CHANNEL SET DISCONNECT CHANNEL SET
EDIT, EDIT AND MARK EXCLUSIVE OR HALT DEVICE HALT I/O INSERT ADDRESS SPACE CONTROL INSERT CHARACTERS UNDER MASK LOAD ADDRESS SPACE PARAMETERS LOAD AND TEST (gen, fl pt) LOAD COMPLEMENT (gen) LOAD COMPLEMENT (fl pt) LOAD NEGATIVE (gen, fl pt) LOAD POSITIVE (gen) LOAD POSITIVE (fl pt) LOAD REAL ADDRESS MOVE LONG MOVE TO PRIMARY, MOVE TO SECONDARY MOVE WITH KEY Zero
Zero
Zero,
o
no carry
Zero
Zero
Zero
Reset signaled
No operation
in progress
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Equal
Successful
Successful
Zero
Zero
Interruption
pending/busy
Interruption
pending
Zero
All zeros Parameters loaded
Zero
Zero
Zero
Zero
Zero
Zero
Translation
available
Length equal
Length =< 256
Length =< 256
APPENDIX CONDITION-CODE SETTINGS
The condition codes for the vector
facility are not included in this appen­
dix. See the pUblication IBM System/370 Vector Operations, SA22-7125, for the
condition codes set by vector
instructions.
Some models may offer instructions which
set the condition code and do not appear
in this document, such as those provided
for assists or as part of special or
custom features.
Condition Code
1
< zero
< zero
Not zero,
no carry
< zero
< zero
Not zero CSW stored
Low
Low
Not equal
Low
Not equal
Low
Low
Low
Connected to
another CPU Connected to
another CPU < zero
Not zero CSW stored
CSW stored One First bit one Primary ASN not available
< zero
< zero
< zero
< zero
ST entry
invalid
Length low
> zero
> zero
Zero,
carry
> zero
> zero
2
Channel busy
Channel busy
High
High
High
High
High
High
> zero
3 Overflow Overflow Not zero,
carry
Not operational
Not operational
Not operational
Not operational Channel Not operational
working
Burst operation Not operational
terminated
First bit zero --
Secondary ASN Space-switch
not available event
or not
authorized
> zero
> zero
> zero
> zero
> zero PT entry
invalid
Length high Overflow Overflow Length
violation
Destructive
overlap
length > 256
Length > 256
Summary of Condition-Code Settings (Part 1 of 2)
Appendix C. Condition-Code Settings C-l

Condition Code
Instruction 0 1 2 3 OR Zero Not zero -- --
RESET REFERENCE BIT, RESET R bit zero, R bit zero, R bit one, R bit one,
REFERENCE BIT EXTENDED C bit zero C bit one C bit zero C bit one
RESUME I/O Successful ----Not operational
SET CLOCK Set Secure --Not operational
SHIFT AND ROUND DECIMAL Zero < zero > zero Overflow SHIFT LEFT (DOUBLE/SINGLE) Zero < zero > zero Overflow
SHIFT RIGHT (DOUBLE/SINGLE) Zero < zero > zero --
SIGNAL PROCESSOR Order accepted Status stored Busy Not operational
START I/O, START I/O FAST Successful CSW stored Busy Not operational
,RELEASE STORE CHANNEL ID ID stored CSW stored Busy Not operational STORE CLOCK Set Not set Error Not operational
SUBTRACT, SUBTRACT HALFWORD Zero < zero > zero Overflow
SUBTRACT DECIMAL Zero < zero > zero Overflow
SUBTRACT LOGICAL --Not zero, Zero, Not zero,
no carry carry carry
SUBTRACT NORMALIZED Zero < zero > zero --
SUBTRACT UNNORMALIZED Zero < zero > zero --
TEST AND SET Left bit zero Left bit one ----
TEST BLOCK Usable Not usable ----
TEST CHANNEL Available Interruption Burst mode Not operational
pending
TEST I/O Available CSW stored Busy Not operational
TEST PROTECTION Can fetch, Can fetch, Cannot fetch, Translation not
can store cannot store cannot store available
TEST UNDER MASK All zeros Mixed --All ones
TRANSLATE AND TEST All zeros Incomplete Complete -- ZERO AND ADD Zero < zero > zero Overflow
EXElanation:
-- Not applicable
> zero Result greater than zero
< zero Result less than zero
=< 256 Equal to, or less than, 256
> 256 Greater than 256
High First operand high
Low First operand low
length Length of first operand
Summary of Condition-Code Settings (Part 2 of 2)
C-2 System/370 Principles of Operation