APPENOIX FACILITIES
Commercial Instruction Set •...•.•••.••••..••••••••••.•.•.. 0-1 Other Facilities •.•..•••••.••.•.••••.•••••••..••••••••.•.• 0-1 Branch and Save .•.....•..•....•......•••••...••••••.•.•. 0-2 Channel Indirect Oata Addressing •...••••..•••.•.••.•.... 0-2 Channel-Set Switching .•......•..••.•••••.....•.•....••.. 0-2 Clear I/O ••...........•.•.•.•.•.•••..•.•...........•.... 0-2 Command Retry •..••..•••••....•..••••••••••..•••.••.••••. 0-2 Conditional Swapping .•••.•.....•••••.•••....••.....••.•. 0-2 CPU Timer and Clock Comparator .•••.•..•.•......•........ 0-2 Direct Control ..•••....•.•.•..•.•.••.•.••••••..•........ 0-2 Dual-Address Space (OAS) •.•.....•••.••••.•.•..••...•..•. 0-2 Extended ........•......•.••.....••....•....••.•..•.....• 0-3 Extended-Precision Floating Point ...................•... 0-3 Extended Real Addressing .....•...•..•......•..•...•.•... 0-3 External Signals ••.....•••....••.•....•••..••••.•••..... 0-3 Fast Release •...•••.•..........•••••.•••.•••...•••..•••. 0-3 Floating Point •.•.•..............•..•..•....•..•.•.•••.. 0-4 Halt Device ..••.•.•...•.•.....•..•.•••••.........•..•... 0-4 I/O Extended Logout .......•..••..••..••....•••.•...••.•. 0-4 Limited Channel Logout ........•••••..•••••..•••.....•.•. 0-4 Move Inverse ...............•...••••.••••...••...••..•... 0-4 Multiprocessing .....................••••...•............ 0-4 PSW-Key Handling •....•.....•••..•.••.•••.••••.•..•..•.•. 0-4 Recovery Extensions ....•.•.....•.••.•••••••••••..•..•... 0-4 Segment Protection ....•...•..••.•....•••..•••..••..•.•.. 0-4 Service Signal ....••.••..••.•....•.•.•................•. 0-4 Start-I/O-Fast Queuing ..•.......•..••••..•.•••.......... 0-4 Storage-Key-Instruction Extensions ....•.........•...•... 0-5 Storage-Key 4K-Byte Block ....•..•....•••••.••....•....•. 0-5 Suspend and Resume ....•........•...•..••................ 0-5 Test Block .......•....................•.......•......... 0-5 Translation ••••.•........•..•...••••.••......•••.•.•••.. 0-5 Vector •...•.•...•..............•.••.•.•.•..••••.••.•..•. 0-5 31-Bi t IOAWs •...••....•.............••.•..•••..•.•.•.••. 0-5 This appendix lists the facilities in
System/370. Every system includes a
CPU, main storage, and the capability
for at least one byte-multiplexer,
block-multiplexer, or selector channel.
The capability may be implemented by
means of a separate physical unit or may
be provided by sharing the physical unit
with the CPU.
control bit (if block multiplexing
is provided), for the interrupt-key
and interval-timer masks, for chan­
nel masks associated with installed
channels, for monitor masks, for
control of installed machine­
check-handling facilities, and for
the IOEL control (if an installed
channel has the I/O-extended-Iogout
facility)
COMMERCIAL INSTRUCTION SET Every CPU incorporates the commercial
instruction set (listed in Appendix B)
and the associated basic computing func­
tions, including: • Byte-oriented operands • General registers • Basic-control (BC) mode • Control registers, with bit posi­
tions for the block-multiplexing- • Key-controlled protection • Interval timer • TOO clock • Basic operator facilities OTHER FACILITIES
Additionally, the following facilities
are available:
Appendix D. Facilities 0-1

BRANCH AND SAVE
Includes the BRANCH AND SAVE (BAS and
BASR) instruction. CHANNEL INDIRECT DATA ADDRESSING
Includes indirect-data-address words and
the associated CCW flag, which facili­
tate storage addressing when virtual
addresses are used. CHANNEL-SET SWITCHING Provides the ability to connect a chan­
nel set to any CPU in a multiprocessing
configuration. It includes the
instructions CONNECT CHANNEL SET and DISCONNECT CHANNEL SET. CLEAR I/O Provides the clear-I/O (CLRIO) function
on a channel when the CLEAR I/O instruc­
tion is executed. When the CLRIO func­
tion is not implemented, CLEAR I/O is
executed as TEST I/O. COMMAND RETRY Provides the capability in a channel to
retry a command without the occurrence
of an I/O interruption. The retry is
initiated by the control unit. CONDITIONAL SWAPPING Includes the instructions COMPARE AND SWAP and COMPARE DOUBLE AND SWAP. CPU TIMER AND CLOCK COMPARATOR Includes the clock comparator, the CPU timer, the associated extensions to
external interruption, control-register
positions for the clock-comparator and CPU-timer masks, and the instructions
SET CLOCK COMPARATOR, STORE CLOCK COMPA­ RATOR, SET CPU TIMER, and STORE CPU TIMER.
D-2 System/370 Principles of Operation DIRECT CONTROL Includes the external-signal facility
and the read-write-direct facility,
which contains the instructions READ DIRECT and WRITE DIRECT. DUAL-ADDRESS SPACE (DAS)
Includes the following:
1. Dual-space control, which includes:
a. An address-space control, PSW bit 16
b. A primary ASN, bits 16-31 of
control register 4
c. A secondary ASN, bits 16-31 of
control register 3
d. A secondary-segment-table
designation, in control regis­
ter 7
2. DAS authorization mechanisms, which
include the following:
a. An extraction-authority
control, bit 4 of control
register 0 b. A PSW-key mask, bits 0-15 of
control register 3
c. A secondary-space control, bit
5 of control register 0 d. A subsystem-linkage control,
bit 0 of control register 5
e. An ASN-translation control, bit
12 of control register 14
f. An authorization index, bits 0-15 of control register 4
g. A space-switch-event-control
bit, bit 31 of control register
1
3. PC-number translation, which uses
the linkage-table designation in
control register 5
4. ASN translation, which uses an
ASN-first-table origin, bits 20-31 of control register 14
5. ASN authorization
6. DAS tracing
7. The following instructions: EXTRACT PRIMARY ASN (EPAR) EXTRACT SECONDARY ASN (ESAR)
INSERT ADDRESS SPACE CONTROL (lAC) INSERT VIRTUAL STORAGE KEY (IVSK)