Real storage Address
PFRA PFRA
without Extended with Extended
Real Addressing Real Addressing Byte Index Size Bit Bit Bit
of Positions No. Positions No. Positions No. Page in Page-of in Page-of in Virtual of
(Bytes) Table Entry Bits Table Entry Bits Address Bits
2K 0-12 13 0-12 13 21-31 11
4K 0-11 12 13, 14, 0-11 14 20-31 12
Segment Number Max Segm Tbl
Size Index of Segment-
of Field Address-Usable Table
Segment Size able Size Length Increment
(Bytes) (Bits) Segments (Bytes) Code (Bytes)
64K 8 256 1,024 15 64
1M 4 16 64 0 64
Page Max Page Tbl
Size of Index Number
Field of Pages
Segment Page Size in Size
(Bytes) (Bytes) (Bits) Segment (Bytes)
64K 2K 5 32 64
64K 4K 4 16 32
1M 2K 9 512 1,024 1M 4K 8 256 512 TRANSLATION PROCESS This section describes the translation
process as it is performed implicitly
before a virtual address is used to
access main storage. The process of
translating the operand address of LOAD REAL ADDRESS and TEST PROTECTION is the same, except that segment-translation
and page-translation exceptions do not
occur; such situations are instead indi­ cated in the condition code.
Translation of the operand address of LOAD REAL ADDRESS also differs in that
the CPU may be in the real mode and the
translation-lookaside buffer is not
used.
Translation of a virtual address is
performed by means of a segment table
and a page table both of which reside in
real storage. It is controlled by the
OAT-mode bit in the PSW and by the
translation parameters in control regis­
ters 0 and 1. When DAS is installed,
translation is also controlled by the
address-space-control bit in the PSW, and the translation parameters also
include control register 7. Page- Usable Table
Length Increment
Code (Bytes)
15 4
15 2
15 64
15 32
Effective Segment-Table Designation
The segment-table designation used for a
particular address translation is called
the effective segment-table designation.
Accordingly, when a primary virtual
address is translated, control register
1 is used as the effective segment-table
designation, and when a secondary virtu­
al address is translated, control
register 7 is used as the effective
segment-table designation. Without DAS,
the term "effective segment-table desig­
nation" is synonymous with "primary
segment-table designation."
The segment-index portion of the virtual
address is used to select an entry from
the segment table, the starting address
and length of which are specified by the
effective segment-table designation.
This entry designates the page table to
be used and, if the segment-protection
facility is installed, provides the
segment-protection bit.
The page-index portion of the virtual
address is used to select an entry from
Chapter 3. Storage 3-27

the page table. This entry contains the leftmost bits of the real address that
represents the translation of the virtu­
al address.
The byte-index field of the virtual
address is used unchanged as the right­
most bit positions of the real address.
If the I bit is one in either the
segment-table entry or the page-table
entry, the entry is invalid, and the
translation process cannot be completed
for this virtual address. A segment­
translation or a page-translation
exception is recognized.
In order to eliminate the delay associ­
ated with references to translation
tables in real storage, the information
3-28 System/370 Principles of Operation
fetched from the tables normally is also
placed in a special buffer, the translation-lookaside buffer (TlB), and
subsequent translations involving the same table entries may be performed by
using the information recorded in the
TLB. The operation of the TlB is
described in the section "Translation­
lookaside Buffer" in this chapter.
Whenever access to real storage is made
during the address-translation process
for the purpose of fetching an entry
from a segment table or page table, key-controlled protection does not
apply.
The translation process, including the effect of the TLB, is shown graphically
in the figure "Translation Process."