for address generation 5-5
instructions for branching on 7-11
into ASN first and second tables
3-13
into authority table 5-18
into entry and linkage tables 5-21
register for 2-4
indicator
check-stop 12-2
load 12-3
manual 12-3
test 12-5 wait 12-6
indirect-data-address flag 13-38
indirect-data-address word (See IDAW)
indirect data addressing (See channel
indirect data addressing)
indirect storage error 11-21
information format 3-3
inhibition of unit of operation 5-10 initial CPU reset 4-34
signal-processor order 4-39
initial microprogram loading (IML),
signal-processor order 4-39
initial-microprogram-loading (IML)
controls 12-2
initial program loading (See IPL) initial program reset 4-34
signal-processor order 4-39
inoperative (signal-processor status)
4-42
input/output (See I/O) INSERT ADDRESS SPACE CONTROL (lAC)
instruction 10-7 INSERT CHARACTER (IC) instruction 7-20 INSERT CHARACTERS UNDER MASK (ICM)
instruction 7-20 examples A-19 INSERT PSW KEY (IPK) instruction 10-8 INSERT STORAGE KEY (ISK) instruction 10-8 INSERT STORAGE KEY EXTENDED (ISKE) instruction 10-9 INSERT VIRTUAL STORAGE KEY (IVSK) instruction 10-10 installation 2-2
instruction address
as a type of address 3-6
handling by DAT 3-22
in BC-mode PSW 4-8
in EC-mode PSW 4-7
in entry-table entry 5-22
validity bit for 11-22
instruction-length code (See ILC)
instruction-processing damage 11-17
resulting in processing backup 11-19
resulting in processing damage 11-20 instructions (See also instruction lists and page
numbers in Appendix B)
backing up of 11-19
classes of 2-3
control 10-2 damage to 11-17,11-20 decimal 8-1
examples A-30 divisible execution of 5-25
ending of 5-8
examples of use A-7
execution of 5-6
fetching of 5-26
access exception for 6-30 PER event for 4-19 PER-event mask for 4-16
floating-point 9-1
examples A-36
format of 5-3 I/O 13-15
general 7-2
examples A-8 I/O (See I/O instructions)
interruptible (See interruptible
instructions)
length of 5-3
list of B-1
modification by EXECUTE instruction
7-19
prefetching of 5-27
privileged 4-6
for control 10-2 for I/O 13-15
semiprivileged 4-6,10-2 sequence of execution 5-2
stepping of (rate control) 12-4
effect on CPU state 4-2
effect on CPU timer 4-28
unprivileged 4-6,7-2
vector 2-4
integer
binary 7-2
address as 5-5
examples A-2
conversion of between hexadecimal and
decimal F-6
decimal 8-2
integral boundary 3-3
interface (See I/O interface)
interface-control check (channel status)
13-72
interlocked update (in tracing) 4-13
interlocked-update storage reference
5-29
interlocks for virtual storage refer-
ences 5-25
intermittent errors 11-5
internal storage 2-3
interrupt key 12-2
external interruption 6-12
interruptible instructions 5-9 COMPARE LOGICAL LONG 7-16
effect on interval timer 4-29 MOVE LONG 7-25 PER event affecting the ending of
4-17
stopping of 4-2 TEST BLOCK 10-51 vector instructions 5-9
interruption 6-2 (See also masks)
action 6-2 I/O 13-62
machine-check 11-12
CAl (channel-available interruption)
13-29,13-61
classes of 6-5
effect on instruction sequence 5-8
external (See external interruption)
machine-check (See machine-check
interruption)
masking of 6-6
pending 6-6
external 6-10 I/O 13-10 machine-check 11-13
relation to CPU state 4-2
priority of (See priority)
program (See program interruption)
imprecise 6-7
Index X-11
program-controlled (See PCI) restart 6-35
string (See string of interruptions)
supervisor-call 6-36
interruption code 6-5
external 6-10 I/O 6-14
in BC-mode PSW 4-8
machine-check (MCIC) 3-44,11-15
program 6-14
summary of 6-2
supervisor-call 6-36
interruption conditions 6-2
clearing of 4-33
floating 6-7,11-27 I/O 13-7,13-60 interruption parameter, external
(assigned storage locations) 3-42
interval timer 4-29
damage 11-17
external interruption 6-12
manual control for 12-3
subclass-mask bit 6-12
update reference 5-33
intervention required (bit in I/O-sense data) 13-51 invalid address 6-15 bit in ASN-first-table entry 3-14
bit in ASN-second-table entry 3-14 bit in linkage-table entry 5-21 bit in page-table entry 3-26
bit in segment-table entry 3-25 cac 11-2
in registers 11-9
in storage 11-6
in storage keys 11-7
channel programs 13-70 operation code 6-21
order (signal-processor status) 4-42
translation address 3-31
translation format 3-24
exception recognition 3-31
INVALIDATE PAGE TABLE ENTRY (IPTE) instruction 10-11 effect of when CPU is stopped 4-2
inverse move (See MOVE INVERSE instruc­
tion, move-inverse facility) IOCA (I/O-communication area) 13-80 address of IOEL (I/O extended logout)
in 13-80 channel ID in 13-32,13-80 I/O address in 13-62,13-83 I/O extended logout in (See IOEL) measurement byte in 13-62,13-83 IOEL (I/O extended logout) 13-80 address of 13-80 assigned storage locations for
3-44
control bit for 11-29
facility D-4
maximum length of 13-32 IPK (INSERT PSW KEY) instruction 10-8 IPL (initial program loading) 4-35
assigned storage locations for 3-41
effect on CPU state 4-3 IPTE (INVALIDATE PAGE TABLE ENTRY) instruction 10-11 ISK (INSERT STORAGE KEY) instruction 10-8 ISKE (INSERT
instruction
IVSK (INSERT
instruction STORAGE KEY EXTENDED) 10-9 VIRTUAL STORAGE KEY) 10-10 X-12 System/370 Principles of Operation K
K (kilo) iv
key
access (See access key)
for I/O (See subchannel key)
manual (See manual operation) PSW (See PSW key)
storage (See storage key)
subchannel (See subchannel key)
key-controlled protection 3-8 exception for 6-23
key handling, provided by DAS 5-16
key mask
L
authorization 5-22
entry 5-22 PSW (PKM) 5-18
L (LOAD) binary instruction 7-20 example A-20 L fields of instruction 5-4
LA (LOAD ADDRESS) instruction 7-21
examples A-20 LASP (LOAD ADDRESS SPACE PARAMETERS) instruction 10-12 late exception recognition 6-9 LCDR (LOAD COMPLEMENT) floating-point
instruction 9-11 LCER (LOAD COMPLEMENT) floating-point
instruction 9-11 LCR (LOAD COMPLEMENT) binary instruction
7-21 LCTL (LOAD CONTROL) instruction 10-20 LD (LOAD) floating-point instruction 9-10 LDR (LOAD) floating-point instruction 9-10 LE (LOAD) floating-point instruction 9-10 left-to-right addressing 3-2
length
field 3-3
instruction 5-3
of I/O block 13-70 (See also count field)
register-operand 5-4
second operand same as first 5-4
variable (storage operand) 5-4
LER (LOAD) floating-point instruction 9-10 lH (LOAD HALFWORD) instruction 7-22
examples A-20 LIFO (last in first out) queuing, exam­
ple for lock and unlock A-43
light (See indicator)
limited channel logout
assigned storage locations for 3-44
facility D-4
format of 13-80 storing of 13-62
link information
for BRANCH AND LINK instruction 7-9
for BRANCH AND SAVE instruction 7-9
linkage for subroutines 5-6
provided by DAS 5-15
linkage index (LX) 5-21
linkage table (LT) 5-21
designation (LTD) 5-21
in AST entry 3-15
Previous Page Next Page