for address generation 5-5
instructions for branching on 7-11
intoASN first and second tables
3-13
into authority table 5-18
into entry and linkage tables 5-21
register for 2-4
indicator
check-stop 12-2
load 12-3
manual 12-3
test 12-5wait 12-6
indirect-data-address flag 13-38
indirect-data-address word(See IDAW)
indirect data addressing(See channel
indirect data addressing)
indirect storage error 11-21
information format 3-3
inhibition of unit of operation5-10 initial CPU reset 4-34
signal-processor order 4-39
initial microprogram loading (IML),
signal-processor order 4-39
initial-microprogram-loading (IML)
controls 12-2
initial program loading(See IPL) initial program reset 4-34
signal-processor order 4-39
inoperative (signal-processor status)
4-42
input/output(See I/O) INSERT ADDRESS SPACE CONTROL (lAC)
instruction10-7 INSERT CHARACTER (IC) instruction 7-20 INSERT CHARACTERS UNDER MASK (ICM)
instruction7-20 examples A-19 INSERT PSW KEY (IPK) instruction 10-8 INSERT STORAGE KEY (ISK) instruction 10-8 INSERT STORAGE KEY EXTENDED (ISKE) instruction 10-9 INSERT VIRTUAL STORAGE KEY (IVSK) instruction 10-10 installation 2-2
instruction address
asa type of address 3-6
handling by DAT 3-22
in BC-modePSW 4-8
in EC-modePSW 4-7
in entry-table entry 5-22
validity bit for 11-22
instruction-length code(See ILC)
instruction-processing damage 11-17
resulting in processing backup 11-19
resulting in processing damage11-20 instructions (See also instruction lists and page
numbers in Appendix B)
backing up of 11-19
classes of 2-3
control10-2 damage to 11-17,11-20 decimal 8-1
examplesA-30 divisible execution of 5-25
ending of 5-8
examples of use A-7
execution of 5-6
fetching of 5-26
access exception for6-30 PER event for 4-19 PER-event mask for 4-16
floating-point 9-1
examples A-36
format of 5-3I/O 13-15
general 7-2
examples A-8I/O (See I/O instructions)
interruptible(See interruptible
instructions)
length of 5-3
list of B-1
modification by EXECUTE instruction
7-19
prefetching of 5-27
privileged 4-6
for control10-2 for I/O 13-15
semiprivileged4-6,10-2 sequence of execution 5-2
stepping of (rate control) 12-4
effect onCPU state 4-2
effect onCPU timer 4-28
unprivileged 4-6,7-2
vector 2-4
integer
binary 7-2
address as 5-5
examples A-2
conversion of between hexadecimal and
decimal F-6
decimal 8-2
integral boundary 3-3
interface(See I/O interface)
interface-control check (channel status)
13-72
interlocked update (in tracing) 4-13
interlocked-update storage reference
5-29
interlocks for virtual storage refer-
ences 5-25
intermittent errors 11-5
internal storage 2-3
interrupt key 12-2
external interruption 6-12
interruptible instructions 5-9COMPARE LOGICAL LONG 7-16
effect on interval timer 4-29MOVE LONG 7-25 PER event affecting the ending of
4-17
stopping of 4-2TEST BLOCK 10-51 vector instructions 5-9
interruption 6-2(See also masks)
action 6-2I/O 13-62
machine-check 11-12
CAl (channel-available interruption)
13-29,13-61
classes of 6-5
effect on instruction sequence 5-8
external(See external interruption)
machine-check(See machine-check
interruption)
masking of 6-6
pending 6-6
external6-10 I/O 13-10 machine-check 11-13
relation toCPU state 4-2
priority of(See priority)
program(See program interruption)
imprecise 6-7
Index X-11
instructions for branching on 7-11
into
3-13
into authority table 5-18
into entry and linkage tables 5-21
register for 2-4
indicator
check-stop 12-2
load 12-3
manual 12-3
test 12-5
indirect-data-address flag 13-38
indirect-data-address word
indirect data addressing
indirect data addressing)
indirect storage error 11-21
information format 3-3
inhibition of unit of operation
signal-processor order 4-39
initial microprogram loading (IML),
signal-processor order 4-39
initial-microprogram-loading (IML)
controls 12-2
initial program loading
signal-processor order 4-39
inoperative (signal-processor status)
4-42
input/output
instruction
instruction
instruction address
as
handling by DAT 3-22
in BC-mode
in EC-mode
in entry-table entry 5-22
validity bit for 11-22
instruction-length code
instruction-processing damage 11-17
resulting in processing backup 11-19
resulting in processing damage
numbers in Appendix B)
backing up of 11-19
classes of 2-3
control
examples
ending of 5-8
examples of use A-7
execution of 5-6
fetching of 5-26
access exception for
floating-point 9-1
examples A-36
format of 5-3
general 7-2
examples A-8
interruptible
instructions)
length of 5-3
list of B-1
modification by EXECUTE instruction
7-19
prefetching of 5-27
privileged 4-6
for control
semiprivileged
stepping of (rate control) 12-4
effect on
effect on
unprivileged 4-6,7-2
vector 2-4
integer
binary 7-2
address as 5-5
examples A-2
conversion of between hexadecimal and
decimal F-6
decimal 8-2
integral boundary 3-3
interface
interface-control check (channel status)
13-72
interlocked update (in tracing) 4-13
interlocked-update storage reference
5-29
interlocks for virtual storage refer-
ences 5-25
intermittent errors 11-5
internal storage 2-3
interrupt key 12-2
external interruption 6-12
interruptible instructions 5-9
effect on interval timer 4-29
4-17
stopping of 4-2
interruption 6-2
action 6-2
machine-check 11-12
CAl (channel-available interruption)
13-29,13-61
classes of 6-5
effect on instruction sequence 5-8
external
machine-check
interruption)
masking of 6-6
pending 6-6
external
relation to
priority of
program
imprecise 6-7
Index X-11