SET PREFIX (SPX) instruction 10-40 SET PROGRAM MASK (SPM) instruction 7-31 SET PSW KEY FROM ADDRESS (SPKA) instruc-
tion 10-41 SET SECONDARY ASN (SSAR) instruction 10-41 trace entry 4-14
set state (of TOD clock) 4-24 SET STORAGE KEY (SSK) instruction 10-45 SET STORAGE KEY EXTENDED (SSKE) instruc- tion 10-45 SET SYSTEM MASK (SSM) instruction 10-46 SH (SUBTRACT HALFWORD) instruction 7-37
shared control unit and subchannel 13-5
shared storage (See storage sharing)
shared TOD clock 4-23
SHIFT AND ROUND DECIMAL (SRP) instruc­
tion 8-10 examples A-34
SHIFT LEFT DOUBLE (SLDA) instruction
7-31
example A-26
SHIFT LEFT DOUBLE LOGICAL (SLDL)
instruction 7-32
SHIFT LEFT SINGLE (SLA) instruction
7-32
example A-26
SHIFT LEFT SINGLE LOGICAL (SLL) instruc­
tion 7-33
SHIFT RIGHT DOUBLE (SRDA) instruction
7-33
SHIFT RIGHT DOUBLE LOGICAl (SRDL)
instruction 7-33
SHIFT RIGHT SINGLE (SRA) instruction
7-34
SHIFT RIGHT SINGLE LOGICAL (SRL)
instruction 7-34
shifting, floating-point (See normal-
ization)
short floating-point number 9-2
short I/O block 13-70 SI instruction format 5-3
sign bit
binary 7-2
floating-point 9-1
sign codes (decimal) 8-2
signal-in lines 6-12
SIGNAL PROCESSOR (SIGP) instruction 10-46 orders 4-38
status 4-41
signed binary
arithmetic 7-3
comparison 7-4
integer 7-2
examples A-2
significance
exception 6-25
loss 9-2
in floating-point addition 9-7
mask in BC-mode PSW 4-8
in EC-mode PSW 4-7
starter (in EDIT) 8-7
SIGP (See SIGNAL PROCESSOR instruction)
single-access reference 5-30 SID (START I/O) instruction 13-27
SID and SIOF functions 13-27 SIOF (START I/O FAST RELEASE) instruc­
tion 13-27
size notation iv
size of segment and page 3-23
optional D-5
skip flag in CCW 13-38
skipping (during I/O) 13-43 SL (SUBTRACT LOGICAL) instruction 7-37 SLA (SHIFT LEFT SINGLE) instruction
7-32
example A-26
SLDA (SHIFT LEFT DOUBLE) instruction
7-31
example A-26
SLDL (SHIFT LEFT DOUBLE LOGICAL) instruction 7-32
SLI (suppress-length indication) flag in CCW 13-38
SLL (SHIFT LEFT SINGLE LOGICAL) instruc-
tion 7-33 SLR (SUBTRACT LOGICAL) instruction 7-37
solid errors 11-5
source
field in limited channel logout
13-81
vector-facility (machine-check condi­
tion) 11-19
source of interruption, identified by
interruption code 6-5 SP (SUBTRACT DECIMAL) instruction 8-11
space-switch event 6-25
as aid in program-problem analysis
5-17
control bit
in ASTE 3-15
in translation 3-24
special-operation exception 6-25- specification exception 6-26
SPKA (SET PSW KEY FROM ADDRESS) instruc-
tion 10-41 SPM (SET PROGRAM MASK) instruction 7-31
SPT (SET CPU TIMER) instruction 10-40 SPX (SET PREFIX) instruction 10-40 SR (SUBTRACT) binary instruction 7-36
SRA (SHIFT RIGHT SINGLE) instruction
7-34
SRDA (SHIFT RIGHT DOUBLE) instruction
7-33
SRDL (SHIFT RIGHT DOUBLE LOGICAL) instruction 7-33
SRL (SHIFT RIGHT SINGLE LOGICAL) instruction 7-34
SRP (SHIFT AND ROUND DECIMAL) instruc­
tion 8-10 examples A-34 SS instruction format 5-3 SSAR (SET SECONDARY ASN) instruction 10-41 SSAR-cp (SET SECONDARY ASN instruction,
to current primary) 10-42 SSAR-ss (SET SECONDARY ASH instruction,
with space switching) 10-42 SSE instruction format 5-3
SSK (SET STORAGE KEY) instruction 10-45 SSKE (SET STORAGE KEY EXTENDED) instruc-
tion 10-45 SSM (SET SYSTEM MASK) instruction 10-46 SSM-suppression-control bit 6-25,10-46 SSTD (secondary segment-table desig-
nat ion) 3-24
SSTL (secondary segment-table length)
3-24 SSTO (secondary segment-table origin)
3-24
ST (STORE) binary instruction 7-34
standalone dump 12-5
standard epoch (for TOD clock) 4-25
STAP (STORE CPU ADDRESS) instruction 10-48 start (CPU)
Index X-19

function 4-2
key 12-4
signal-processor order 4-39
START I/O (SIO) instruction 13-27
start-I/O-fast queuing 13-28
facility D-4
initiation of pending I/O operations
13-29,13-55
START I/O FAST RELEASE (SIOF) instruc­
tion 13-27
state CPU (See CPU state) I/O-system (See I/O-system state) TOD-clock 4-24
status
for SIGNAL PROCESSOR 4-38,10-47 in CSW 13-63
contents of 13-78
of channel (See channel status)
of device (See unit status)
program (See PSW) resulting from signal-processor
orders 4-41
storing of 4-37
manual key for 12-5
status modifier (unit status) 13-64 STC (STORE CHARACTER) instruction 7-34 STCK (STORE CLOCK) instruction 7-35 STCKC (STORE CLOCK COMPARATOR) instruc-
tion 10-47 STCM (STORE CHARACTERS UNDER MASK)
instruction 7-35
examples A-26 STCTL (STORE CONTROL) instruction 10-48 STD (segment-table designation) 3-24 STD (STORE) floating-point instruction
9-14 STE (STORE) floating-point instruction
9-14 STH (STORE HALFWORD) instruction 7-36 STIDC (STORE CHANNEL ID) instruction
13-32 STIDP (STORE CPU ID) instruction 10-48 STL (segment-table length) 3-24 STM (STORE MULTIPLE) instruction 7-36
example A-27 STNSM (STORE THEN AND SYSTEM MASK)
instruction 10-50 STO (segment-table origin) 3-24
stop
function 4-2
key 12-4
signal-processor order 4-39
stop and store status (signal-processor
order) 4-39
stopped (signal-processor status) 4-41
stopped state
of CPU 4-2
effect on completion of store
operations 5-29
of TOD clock 4-24
storage 3-2
absolute 3-5
address wraparound (See wraparound)
addressing 3-2
(See also address)
alteration manual controls 12-2
alteration PER event 4-19
mask for 4-16
assigned locations in 3-41
auxiliary 3-2,3-20 block 3-5
testing for usability of 10-50 buffer (cache) 3-2 X-20 System/370 Principles of Operation clearing of (See clearing operation)
concurrency of access for references
to 5-31
configuration of 3-5
direct-access 3-2
display 12-2
error 11-20 indirect 11-21
failing address in (See failing-storage address)
interlocked update 5-29
interlocks for virtual references
5-25
internal 2-3
main 3-2
noninterlocked update 5-29
nonvolatile 3-2
operand 5-4
reference to (fetch, store,
update) 5-29
update reference 5-29
operand consistency 5-30 examples A-44,A-47
prefixing for 3-11
real 3-5
sequence of references to 5-24
size
notation for iv
of segment and page in 3-23
size of segment and page D-5
validation of 11-6
virtual 3-20 volatile 3-2
effect of power-on reset on 4-35
storage-area designation
for I/O operations 13-39
as specified in data-chained CCWs 13-42
as specified in IDAWs 13-45
for PER events 4-18
storage-control unit (in limited channel
logout) 13-81
storage degradation (machine-check
condition) 11-21
storage key 3-6
error in 11-21
sequence of references to 5-28
testing for usability of 10-50 validation of 11-7
storage-key exception-control bit
3-7,6-26
storage-key-instruction extensions 3-7
facility D-5
storage-key 4K-byte-block facility
D-5,3-7
storage-logical-validity bit 11-23
storage protection 3-7
storage sharing
by address spaces 3-20 by CPUs and channels 3-5
examples A-40 in multiprocessing 4-38 STORE (ST) binary instruction 7-34 STORE (STD,STE) floating-point
instructions 9-14 STORE CHANNEL ID (STIDC) instruction
13-32 STORE CHARACTER (STC) instruction 7-34 STORE CHARACTERS UNDER MASK (STCM) instruction 7-35
examples A-26 STORE CLOCK (STCK) instruction 7-35 STORE CLOCK COMPARATOR (STCKC) instruc­
tion 10-47