STORE CONTROL (STCTl) instruction 10-48 STORE CPU ADDRESS (STAP) instruction 10-48 STORE CPU ID (STIDP) instruction 10-48 STORE CPU TIMER (STPT) instruction 10-49 STORE HAlFWORD (STH) instruction 7-36 STORE MULTIPLE (STM) instruction 7-36 example A-27 STORE PREFIX (STPX) instruction 10-49 store reference 5-29
access exceptions for 6-30 store status 4-37 key 12-5
signal-processor order for 4-39 STORE THEN AND SYSTEM MASK (STNSM)
instruction 10-50 STORE THEN OR SYSTEM MASK (STOSM) instruction 10-50 STOSM (STORE THEN OR SYSTEM MASK)
instruction 10-50 STPT (STORE CPU TIMER) instruction 10-49 STPX (STORE PREFIX) instruction 10-49 string of interruptions 4-3,6-37
caused by clock comparator 4-27
caused by CPU timer 4-28 SU (SUBTRACT UNNORMALIZED) instruction
9-15
subchannel 13-4
not operational (I/O-system state)
13-11
working (I/O-system state) 13-11
subchannel key in CAW 13-37
in CSW 13-63
contents of 13-73
validity flag for 13-82
used as access key 3-9
used for IPL 4-36
subclass-mask bits 6-6
external-interruption 6-10 machine-check 11-27
subroutine linkage 5-6
subsystem-linkage-control bit 5-18,5-21
subsystem reset 4-34 SUBTRACT (S,SR) binary instructions
7-36 SUBTRACT DECIMAL (SP) instruction 8-11 SUBTRACT HALFWORD (SH) instruction 7-37 SUBTRACT LOGICAL (SL,SLR) instructions
7-37 SUBTRACT NORMALIZED (SD,SDR,SE,SER,SXR)
instructions 9-14 SUBTRACT UNNORMALIZED (SU,SUR,SW,SWR) instructions 9-15
successful-branching PER event 4-19
mask for 4-16 SUPERVISOR CALL (SVC) instruction 7-38
supervisor-call interruption 6-36
supervisor state 4-6
suppress-Iength-indication (SLI) flag in CCW 13-38
suppression
exceptions to 5-11
of instruction execution 5-9
of unit of operation 5-10 SUR (SUBTRACT UNNORMALIZED) instruction
9-15
suspend-and-resume facility D-5,13-7
suspended (bit in CSW) 13-63,13-74
suspension of channel-program execution
13-28,13-46
suspend (S) flag in CCW 13-7,13-38
suspend-control bit in CAW 13-7,13-37 suspended bit in CSW 13-63
meaning of 13-74 SVC (SUPERVISOR CALL) instruction 7-38 SW (SUBTRACT UNHORMALIZED) instruction
9-15
swapping
by COMPARE (DOUBLE) AND SWAP instructions 7-12
by EXCLUSIVE OR instruction 7-18
switching of channel sets 4-43
SWR (SUBTRACT UNNORMALIZED) instruction
9-15
SX (segment index) 3-21
SXR (SUBTRACT NORMALIZED) instruction
9-14
synchronization
checkpoint 11-3
of CPU timer with TOD clock 4-28
of TOD clocks 4-24,4-26
synchronous logout 11-28
synchronous machine-check
extended-Iogout-control bit 11-29
synchronous machine-cheek-interruption
conditions 11-19
system
manual control of 12-1
organization of 2-1
system check stop 11-11
system damage 11-16
system mask (in PSW) 4-3
validity bit for 11-22
system recovery 11-17
system reset (See reset) system-reset-clear key 12-5
system-reset-normal key 12-5
T
table of powers of 2 E-l
tables
ASN (See ASN first table, ASN second
table)
authority (See authority table)
DAT (See page table, segment table)
entry (See entry table)
hexadecimal F-1
linkage (See linkage table)
page (See page table)
segment (See segment table)
translation 3-25
target instruction 7-19
TB (TEST BLOCK) instruction 10-50 TCH (TEST CHANNEL) instruction 13-33
termination
of 1/0 operations (See also conclusion of I/O oper-
ations)
by channel or device 13-56
by CLEAR CHANNEL 13-59
by CLEAR 1/0 13-59
by HALT DEVICE 13-57 due to equipment malfunction
13-59
of instruction execution 5-9
for exigent machine-check condi­
tions 11-11
of unit of operation 5-10 for exigent machine-check condi­
tions 11-11
termination code (in limited channel
logout) 13-82
Index X-21

TEST AND SET (TS) instruction 7-38 TEST BLOCK (TB) instruction 10-50 test-block facility 0-5,10-50 TEST CHANNEL (TCH) instruction 13-33 TEST I/O (TIO) instruction 13-34 function performed by CLEAR I/O instruction 13-17
test indicator 12-5 TEST PROTECTION (TPROT) instruction 10-52 TEST UNDER MASK (TM) instruction 7-38 examples A-27
testing for storage-block and
storage-key usability 10-50 TIC (transfer-in-channel) I/O command 13-53 time-of-day clock (See TOO clock)
timeout
bits in external-damage code 11-25
channel 13-4
timer CPU (See CPU timer)
interval (See interval timer)
timing facilities 4-23
timing-facility damage 11-17
for TOO clock 4-25 TIO (TEST I/O) instruction 13-34
TLB (translation-lookaside buffer) 3-31
entries 3-32
attachment of 3-32
clearing of 3-36
effect of translation changes on
3-36
usable state 3-32
summary 3-33
TM (TEST UNDER MASK) instruction 7-38
examples A-27 TOO clock 4-23 effect of power-on reset on 4-35
effect on clock-comparator inter­
ruption 6-11 effect on CPU-timer decrementing
4-28 effect on CPU-timer interruption
6-11 effect on interval-timer decrementing
4-29
effect on interval-timer inter-
ruptions 6-12
manual control of 4-24,12-5
unique values of 4-25
validation of 11-9 TOO-clock sync check (external inter-
ruption) 6-13
TOD-clock-sync-control bit 4-24,4-27
TOD-clock-synchronization facility 4-26 TPROT (TEST PROTECTION) instruction 10-52 TR (TRANSLATE) instruction 7-39
example A-28
trace-entry formats 4-14 trace exceptions 6-35
tracing 4-11
for program-problem analysis 5-17 header 4-13
transfer-in-channel (TIC) I/O command
13-53
TRANSLATE (TR) instruction 7-39
example A-28
TRANSLATE AND TEST (TRT) instruction 7-40 example A-28
translation
address 3-20 X-22 System/370 Principles of Operation (See also dynamic address trans-
lation) ASH 3-12
exception identification 3-43 facility D-S
format 3-23
lookaside buffer (See TlB)
modes 3-22
parameters 3-22 PC-number 5-21
specification exception 6-27
tables for 3-25
trial execution
for editing instructions and TRANS­ LATE instruction 5-12
for PER 4-16
TRT (TRANSLATE AND TEST) instruction 7-40 example A-28
true zero (floating-point number) 9-1 TS (TEST AND SET) instruction 7-38
two's complement binary notation 7-2
examples A-2
U
underflow (See exponent underflow)
unit check (unit status) 13-68
unit exception (unit status) 13-69
unit of operation 5-9
unit status 13-63
attention 13-64
busy 13-65
channel end 13-67
control-unit end 13-64
device end 13-67
status modifier 13-64
unit check 13-68
unit exception 13-69
validity flag for 13-82
universal instruction set 0-4 unlock A-42
example with FIFO queuing A-45
example with LIFO queuing A-44
unnormalized floating-point number 9-2
unnormalized-operand exception 6-27 UNPACK (UNPK) instruction 7-40 example A-30 UNPK (UNPACK) instruction 7-40 example A-30 unprivileged instructions 4-6,7-2
unsigned binary
arithmetic 7-3
integer 7-2
examples A-4
in address generation 5-5
update reference 5-29
usable TLB entry 3-32 V valid CBC 11-2
valid segment-table or page-table entry
3-32
validation 11-5
of registers 11-9
of storage 11-6
of storage key 11-7
of TOO clock 11-9
validity bits, in
machine-check-interruption code 11-21