validity flags (in limited channel
logout) 13-82
variable-length field 3-3
vector facility 0-5,2-4 effect of power-on reset on 4-35
vector-facility failure (machine-check
condition) 11-18
vector-facility source (machine-check
condition) 11-19
vector-operation exception 6-28
vector operations, publication refer-
enced v
version code 10-48 virtual address 3-5
virtual storage 3-20 volatile storage 3-2
effect of power-on reset on 4-35 W WAIT (SVC), example of routine to bypass
A-42
wait indicator 12-6
wait-state bit
in BC-mode PSW 4-8
in EC-mode PSW 4-6
warning (machine-check condition) 11-18
subclass-mask bit for 11-28
word 3-3
word-concurrent storage references 5-31
wraparound
of instruction addresses 5-5
of PER addresses 4-18
of register numbers
for LOAD MULTIPLE instruction
7-22
for STORE MULTIPLE instruction
7-36
of storage addresses 3-2
for MOVE INVERSE instruction 7-24
for MOVE LONG instruction 7-25
of TOO clock 4-24
WRD (WRITE DIRECT) instruction 10-54 write (I/O command) 13-49
WRITE DIRECT (WRD) instruction 10-54 x
X (EXCLUSIVE OR) instruction
X field of instruction 5-5 XC (EXCLUSIVE OR) instruction
examples A-17
XI (EXCLUSIVE OR) instruction
example A-18
XR (EXCLUSIVE OR) instruction Z ZAP (ZERO AND ADD) instruction
example A-36
zero
7-18
7-18
7-18
7-18
8-12
instruction-length code 6-7
negative (See negative zero)
normal meaning for byte value
true (floating-point number) iv 9-1
8-12 ZERO AND ADD (ZAP) instruction
example A-36
zone bits 8-1
moving of 7-28
zoned decimal numbers 8-1
examples A-5
3
31-bit IDAW (indirect-data-address word)
facility 13-46
Index X-23
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