code is stored
134-135.
136-139(Real Address) at locations
Supervisor-CalI-Interruption
Identification: Duringa supervisor-call interruption in
the EC mode, the instruction
length code is stored in bit
positions 5 and 6 of location
137, and the interruption code
is storedat locations 138-139. Zeros are stored at location 136
and in theremaining bit posi tions of location 137. 140-143 (Real Address)
Proqram-Interruption Identifi
cation: Duringa program inter
ruptionin the EC mode, the
instruction-length code is
stored inbit positions 5 and 6
of location 141, and the inter
ruption code is stored at
locations 142-143.Zeros are
stored at location140 and in
theremaining bit positions of
location 141.
144-147 (Real Address)
Translation-Exception Identifi
cation: During a program inter
ruptiondue to a segment
translation exception ora page-translation exception, the
segment-index and page-index
portion of the virtual address
causing the exceptionis stored at locations 144-147. This
address is sometimes referred toas the translation-exception
address. When 2K-byte pages are
used, the rightmost 11 bits of
the address are unpredictable.
When 4K-byte pages are used, the
rightmost 12bits of the address
are unpredictable. Bits 1-7 of
location 144 are set to zeros.
When DAS is installed,bit 0 of
location 144is set to zero if
the translation was relative to
the primary segment table desig
nated by control register 1, or
it is set to one if the trans
lation was relative to the
secondary segment table desig
nated by control register 7.
When DAS is not installed,bit 0 of location 144 is set to zero.
Duringa program interruption due to an AFX-translation, ASX
translation, primary-authority,
or secondary-authority excep
tion, theASN being translated
is storedat locations 146-147. Zeros are stored at locations
144-145.
Duringa program interruption
fora space-switch event, the
oldPASN, which is in bits 16-31
of control register 4 before the
execution of a space-switchingPROGRAM CALL or PROGRAM TRANSFER
instruction, is stored at
locations 146-147. The old
space-switch-event-control bitis stored in bit position 0, and
zeros are stored in bit posi
tions 1-15 of locations 144-145.
Duringa program interruption
due toan LX-translation or EX
translation exception, the PC
number is stored in bit positions 12-31 of the word at
locations 144-147. Bits0-11 are set to zeros.
In all
locations
when the
EC mode.
cases,
144-147
old PSW
148-149 (Real Address)
storing at
only occurs
specifies the
Monitor-Class Number: Duringa program interruption due to a
monitor event, the monitor-class
number is stored at location
149, and zeros are storedat location 148. 150-151 (Real Address)
PER Code: During a program
interruption due toa PER event,
the PER codeis stored in bit positions 0-3 of location 150. Zeros are stored in bit posi
tions 4-7 of location150 and
bit positions0-7 of location
151. This field can be stored
only when the instruction caus
ing the PER condition was
executed under the control ofa PSW specifying the EC mode.
152-155 (Real Address)
PER Address: During a program
interruption due to a program
event, the PER address is stored
at locations 153-155, and zeros
are storedat location 152.
This field can be stored only
when the instruction causing the
PER condition was executed under
the control ofa PSW specifying
the EC mode.
156-159 (Real Address)
Monitor Code: During a program
interruption due to a monitor
event, the monitor code is
stored at locations 157-159, and
zeros are storedat location
156.
Chapter 3. storage 3-43
134-135.
136-139
Supervisor-CalI-Interruption
Identification: During
the EC mode, the instruction
length code is stored in bit
positions 5 and 6 of location
137, and the interruption code
is stored
and in the
Proqram-Interruption Identifi
cation: During
ruption
instruction-length code is
stored in
of location 141, and the inter
ruption code is stored at
locations 142-143.
stored at location
the
location 141.
144-147 (Real Address)
Translation-Exception Identifi
cation: During a program inter
ruption
translation exception or
segment-index and page-index
portion of the virtual address
causing the exception
address is sometimes referred to
address. When 2K-byte pages are
used, the rightmost 11 bits of
the address are unpredictable.
When 4K-byte pages are used, the
rightmost 12
are unpredictable. Bits 1-7 of
location 144 are set to zeros.
When DAS is installed,
location 144
the translation was relative to
the primary segment table desig
nated by control register 1, or
it is set to one if the trans
lation was relative to the
secondary segment table desig
nated by control register 7.
When DAS is not installed,
During
translation, primary-authority,
or secondary-authority excep
tion, the
is stored
144-145.
During
for
old
of control register 4 before the
execution of a space-switching
instruction, is stored at
locations 146-147. The old
space-switch-event-control bit
zeros are stored in bit posi
tions 1-15 of locations 144-145.
During
due to
translation exception, the PC
number is stored in bit posi
locations 144-147. Bits
In all
locations
when the
EC mode.
cases,
144-147
old PSW
148-149 (Real Address)
storing at
only occurs
specifies the
Monitor-Class Number: During
monitor event, the monitor-class
number is stored at location
149, and zeros are stored
PER Code: During a program
interruption due to
the PER code
tions 4-7 of location
bit positions
151. This field can be stored
only when the instruction caus
ing the PER condition was
executed under the control of
152-155 (Real Address)
PER Address: During a program
interruption due to a program
event, the PER address is stored
at locations 153-155, and zeros
are stored
This field can be stored only
when the instruction causing the
PER condition was executed under
the control of
the EC mode.
156-159 (Real Address)
Monitor Code: During a program
interruption due to a monitor
event, the monitor code is
stored at locations 157-159, and
zeros are stored
156.
Chapter 3. storage 3-43