special-operation exception if execution
is attempted in the BC mode: EXTRACT PRIMARY ASN EXTRACT SECONDARY ASN INSERT ADDRESS SPACE CONTROL INSERT VIRTUAL STORAGE KEY MOVE TO PRIMARY MOVE TO SECONDARY PROGRAM CAll PROGRAM TRANSFER
SET ADDRESS SPACE CONTROL SET SECONDARY ASN Programming Notes
1. The BC mode provides a PSW format
that is compatible with the PSW of
System/360.
2. The choice between the EC and BC modes affects only those aspects of
operation that are specifically
defined to be different for the two
modes. It does not affect the
operation of any functions that are
not associated with the PSW control
bits provided only in the EC mode,
and, except for those listed above,
it does not affect the validity of
any instructions. The instructions
SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and STORE THEN OR SYSTEM MASK perform the specified
function on the leftmost byte of
the PSW regardless of the mode
specified by the current PSW. On the other hand, the instruction SET PROGRAM MASK introduces a new
program mask regardless of the PSW bit positions occupied by the mask. Chapter 4. Control 4-5

PROGRAM-STATUS-WORD FORMAT IN EC MODE 0 o 0 0 0 0 0 0 0 5 8 12 16 18 20 24 31 10 o 0 0 0 0 0 01 Instruction Address
32 40 PSW Format in EC Mode
The following is a summary of the func­
tions of the PSW fields in the EC mode. (See the figure "PSW Format in EC ~'ode.") PER Mask (R)~ Bit 1 controls whether
the -CPU is enabled for interruptions aS50ciated with program-event recording (PER). When the bit is zero, no PER event can cause an interruption. When
the bit is one, interruptions are
permitted, subject to the PER-event-mask
bits in control register 9.
DAT Mode (I): Bit 5 controls whether implicit dynamic address translation of
logical and instruction addresses used to access storage takes place. When the bit is zero, DAT is off, and logical and
instruction addre5ses are treated as real addresses. When the bit i5 one, DAT is on, and the dynamic-address­
translation mechanism is invoked. I/O Mask (10): Bit 6 controls whether the -CPU is--enabled for I/O interrup­
tions. When the bit is zcro, an I/O interruption cannot occur. When the bit
is one, I/O interruptions are subject to thC! channel-mask bits in control regis­ ter 2. When a channel-mask bit is zero, the associated channel CC1nnot caU::iQ.un I/O interruption; wh~n the channel-mask bit is one, an interruption condition at the channel can cause an interruption. Bit 6 0 f the E C
- r:1O de P S L,J i s p t~ 0 v ide d evan when the CPU is not capable of being connected to a channel set. Ext~rnal Mask (EX): Bit 7 controls whathel' the-CPU 1; enabled for i nter­ rllPtion by conditions included in the ext ern a 1 cIa 5 s . l·J hen the bit i s Z Q,' 0 , an external interruption cannot occur. When the bit is one, an external inter­ ruption is subject to the corresponding
external subclass-mask bits in control
register 0; when the subclass-ma5k bit is zero, conditions associated with the
subclass cannot cause an interruption; when the subclass-mask bit is one, an
interruption in that subclas5 can occur.
4-6 System/370 Principles of Operation 63 PSW Key: Bits 8-11 form the access key
for storage references by the CPU. If the reference is subject to key­
controlled protection, the PSW key is matched with a storage key when informa­
tion is stored or when information is
fetched from a location that is
protected against fetching. However,
for accesses to the second operand of MOVE TO PRIMARY and MOVE WITH KEY, the
third operand is used instead of the PSW key. The third operand is also used instead of the PSW key for accesses to
the first operand of MOVE TO SECONDARY. EC Mode (1;): Bi t 12, whi ch controls the
format of the PSW and the mode of opera­
tion of the CPU, is one when the CPU is in the extended-control (EC) mode. Machine-Check Mask (M): Bit 13 controls
whether the cFul s enabled for i nter­
ruption by machine-check conditions. When the bit is zero, a machine-check
interruption cannot occur. When the bit is one, machine-check interruptions due
to system dDmage and instruction­
processing damage are permitted, but
interruptions due to other machine­
check-subclass conditions are subject to the subclass-mask bits in control regis­ ter 14. L,J<:!.ii Stab~ (~): l.Jhen bi t l{t is one, the CPU is waiting; that is, no instructions are processed by the CPU, but inter­
ruptions may take place. When bit 14 is zero, instt'uction fetching and execution occur in the normal manner. The wait indicator is on when the bit is one. Proble"! State (f): When bit 15 is one, the CPU is in the problem state. When bit 15 is zero, the CPU is in the super­ visor state. In the supervisor state, all instructions are valid. In the
problem state, only those instructions
are valid that provide meaningful infor­
mation to the problem program and that
cannot affect system integrity; such instructions are called unprivileged
instructions. The instructions that are ~ never valid in the problem state are ~ called privileged instructions. When a