CPU in the problem state attempts to
execute a privileged instruction, a privileged-operation exception is recog­
nized. Another group of instructions,
called semiprivileged instructions, are executed by a CPU in the problem state
only if specific authority tests are
met; otherwise, a privileged-operation
exception or a special-operation excep­
tion is recognized.
Address-Space Control Bi t 16, in
conjunction with PSW bit 5, controls the translation mode. This bit is provided
with DAS. See the section "Translation Modes" under "Translation Control" in Chapter 3, "Storage." Condition Code (CC): Bits 18 and 19 are the two bits of the condition code. The
condition code is set to 0, 1, 2, or 3,
depending on the result obtained in executing certain instructions. Most arithmatic and logical operations, as
well as some other operations, set the condition code. The instruction BRANCH ON CONDITION can specify any selection
of the condition-code values as a crite­ rion for branching. A table in Appendix C summarizes the condition-code values that may be set for all instructions
which set the condition code of the PSW. Prooram Mask: Bits 20-23 are the four program-mask bits. Each bit is associ­ ated with a program exception, as
follows: Program- Mask Bit Program Exception 20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
When the mask bit is one, the exception
results in an interruption. When the
mask bit is zero, no interruption
occurs. The setting of the exponent-
underflow-mask bit or the significance­
mask bit also determines the manner in
which the operation is completed when
the corresponding exception occurs. The
exponent-underflow and significance mask bits are provided in the PSW even when the floating-point facility is not
installed.
Instruction Address: Bits 40-63 form
the instruction address. This address
designates the location of the leftmost
byte of the next instruction to be
executed, unless the CPU is in the wait
state (bit 14 of the PSW is one).
Bit positions 0, 2-4, 17, and 24-39 are
unassigned and must contain zeros. A
specification exception is recognized
when these bit positions do not contain
zeros. Chapter 4. Control 4-7

PROGRAM-STATUS-WORD FORMAT IN Be MODE Chan Masks 0-5 Interruption Code 0 6 8 12 16 31 Prog Inclcc Mask Instruction Address
32 34 36 40 PSW Format in BC Mode
The following is a summary of the func­
tions of the PSW fields in the BC mode. (See the figure "PSW Format in BC Mode.") Channel Masks 0-5: Bits 0-5 control
whether the CPU is enabled for I/O interruptions from channels 0-5, respec­ tively. When a bit is zero, the associ­ ated channel cannot cause an I/O interruption. When the bit is one, an
interruption condition at the channel can cause an I/O interruption. Bits 0-5 of the BC-mode PSW are provided even
when the CPU is not capable of being connected to a channel set. ILQ Mask (lQ): Bit 6 controls whether the CPU is enabled for I/O interruptions
from channels 6 and higher. When the bit is zero, these channels cannot cause I/O interruptions. When the bit is one, I/O interruptions are subject to the channel-mask bits of the corresponding
channels in control register 2. When a
channel-mask bit is zero, the associated channel cannot cause an I/O interruption; when the channel-mask bit is one, an interruption condition at the channel can cause an interruption. Bit 6 of the BC-mode PSW is provided even when the CPU is not capable of being
connected to a channel set. External Mask (EX): The meaning of bit
7 is the same as in the EC mode. PSt.J Key: The meani ng of bi ts 8-11 is the same as in the EC mode. EC Mode (!;): Bit 12, which controls the
format of the PSW and the mode of opera­
tion of the CPU, is zero when the CPU is
in the basic-control (BC) mode. Machine-Check tl;)sk (!1): bit 13 is the same as in The meaning of
the EC mode. LJai t State (W): The meani ng of bi t 14 lSthe same as in the EC mode. Problem State (E): The meaning of bit 151 s -thesame as in the EC mode.
4-8 System/370 Principles of Operation 63
Interruption Code: Bits 16-31 in the
old PSW, when stored during a program,
supervisor-call, external, or I/O inter­
ruption, identify the cause of the
interruption. This field is not used or checked in the current PSW. When a new PSW is introduced, the contents of this field are ignored. Instruction-Len.9.i.b Code (ILC): Bit positions 32 and 33 of the old PSW indi­ cate the length of the last-interpreted
instruction when a program or
supervisor-call interruption occurs. See the section "Instruction-Length Code" in Chapter 6, "Interruptions."
When a new PSW is introduced, the
contents of this field are ignored. Condition Code (CC): Bits 34 and 35 are
the two b1 ts of the condi ti on code. The meaning of the condition code is the
same as in the EC mode. PrOQram Mask: Bits 36-39 are the four program-musk bits. Each bit is associ­ ated with a program exception, as
follows: Program- Mask Bit Program Exception
36 Fixed-point overflow
37 Decimal overfloLoJ 38 Exponent underflow
39 Significance The meaning of each mask bit
as in the EC mode.
Instruction Address: The bits 40-63 is the same as
mode. CONTROL REGISTERS
is the same meaning of
in the EC The control registers provide for main­ taining and manipulating control infor-