In some models, performance of address
range checkingis assisted by means of
anextension to each page-table entry in
theTlD. In such an implementation,
changing the contents of control regis
ters10 and 11 when the instruction
fetching or storage-alteration-event
mask is one, or setting either of thesePER-event masks to one, may cause the
TlB to beclQared of entries. This
degradation may beexperiencQd even when the CPU is disabled for PER events.
Thus, when possible, the program should
avoid loading control registers 9,10, or 11. PER EVENTS
Successful Branching
A successful-branching event occurs
whenever one of the following instruc
tions causes branching:BRANCH AND lINK (BAl, BALR) BRANCH AND SAVE (BAS, BASR) BRANCH ON CONDITION (BC, BCR) BRANCH ON COUNT (BCT, BCTR) BRANCH ON INDEX HIGH (BXH) BRANCH ON INDEX lOW OR EQUAL (BXlE)
A successful-branching event also occurs
whenever one of the following
instructions is completed:PROGRAM CALL (PC) PROGRAM TRANSFER (PT) A successful-branching event causes a PER successful-branching event to be
recognized if bit0 of the PER-event masks is one and the PER mask in the EC-mode PSW is one.
APER successful-branching event is indicated by setting bit 0 of the PER code to one.
Instruction Fetching
An instruction-fetching event occurs if
the first byte of the instruction is
fetched from the storage area designated
by control registers10 and 11. An
instruction-fetching event also occurs
if the first byte of the target ofEXECUTE is within the designated storage
area. An instruction-fetching event causes a , PER i nstructi on-fetchi ng event to be
recognized if bit 1 of thePER-event masks;s one and the PER mask in the EC-mode PSW is one.
ThePER instruction-fetching event is
indicated by setting bit 1 of thePER code to one.
Storage Alteration
A storage-alteration event occurs when
ever aCPU, by using a logical or virtu
al address, makes a store access withoutan access exception to the storage area designated by control registers 10 and 11 .
The contents of storage are considered
to havebeen altered whenever the CPU executes an instruction that causes all
orpart of an operand or a DAS-trace
value tobe stored within thQ designated storage area. Alteration is considered to take place whenever storing is
considered totake place for purposes of
indicating protection exceptions, exceptthat recognition does not occur for the
storing of data by a channel program.
(See the section"Recognition of Access Exceptions" in Chapter 6, "Interrup tions.") Storing constitutes alteration
forPER purposes even if the value
stored is the sameas the original
value.
Implied locationsthat are referred to
by theCPU in the process of
(1) interval-timer updating,
(2) interruptions, and (3) execution ofI/O instructions are not monitored.
Such locations include the interval
timer,old-PSW, interruption-code, and CSW locations. These locations,
however, are monitored when information
is stored there explicitly byan instruction. Similarly, monitoring does
not apply to the storing ofdata by a
channel program.
Whenan interruptible vector instruction
which performs storing is interrupted,
andPER storage alteration applies to
storage locations corresponding to
elements due to be changed beyond the
point of interruption,PER storage
alterationis indicated if any such
store actually occurred and may be indi
cated even if such a store did not
occur.PER storage alteration is
reported for such locations only if no
access exception exists at the time that
the instruction is executed.
Storage alteration does not apply to
instructions whose operands are speci
fied to be real addresses. Thus, storage alteration does not apply to
INVALIDATEPAGE TABLE ENTRY, RESET REFERENCE BIT, RESET REFERENCE BIT
EXTENDED,SET STORAGE KEY, SET STORAGE KEY EXTENDED, and TEST BLOCK. When
INVALIDATEPAGE TABLE ENTRY is Chapter 4. Control 4-19
range checking
an
the
changing the contents of control regis
ters
fetching or storage-alteration-event
mask is one, or setting either of these
TlB to be
degradation may be
Thus, when possible, the program should
avoid loading control registers 9,
Successful Branching
A successful-branching event occurs
whenever one of the following instruc
tions causes branching:
A successful-branching event also occurs
whenever one of the following
instructions is completed:
recognized if bit
A
Instruction Fetching
An instruction-fetching event occurs if
the first byte of the instruction is
fetched from the storage area designated
by control registers
instruction-fetching event also occurs
if the first byte of the target of
area.
recognized if bit 1 of the
The
indicated by setting bit 1 of the
Storage Alteration
A storage-alteration event occurs when
ever a
al address, makes a store access without
The contents of storage are considered
to have
or
value to
considered to
indicating protection exceptions, except
storing of data by a channel program.
(See the section
for
stored is the same
value.
Implied locations
by the
(1) interval-timer updating,
(2) interruptions, and (3) execution of
Such locations include the interval
timer,
however, are monitored when information
is stored there explicitly by
not apply to the storing of
channel program.
When
which performs storing is interrupted,
and
storage locations corresponding to
elements due to be changed beyond the
point of interruption,
alteration
store actually occurred and may be indi
cated even if such a store did not
occur.
reported for such locations only if no
access exception exists at the time that
the instruction is executed.
Storage alteration does not apply to
instructions whose operands are speci
fied to be real addresses. Thus, stor
INVALIDATE
EXTENDED,
INVALIDATE