In some models, performance of address­
range checking is assisted by means of
an extension to each page-table entry in
the TlD. In such an implementation,
changing the contents of control regis­
ters 10 and 11 when the instruction­
fetching or storage-alteration-event
mask is one, or setting either of these PER-event masks to one, may cause the
TlB to be clQared of entries. This
degradation may be experiencQd even when the CPU is disabled for PER events.
Thus, when possible, the program should
avoid loading control registers 9, 10, or 11. PER EVENTS
Successful Branching
A successful-branching event occurs
whenever one of the following instruc­
tions causes branching: BRANCH AND lINK (BAl, BALR) BRANCH AND SAVE (BAS, BASR) BRANCH ON CONDITION (BC, BCR) BRANCH ON COUNT (BCT, BCTR) BRANCH ON INDEX HIGH (BXH) BRANCH ON INDEX lOW OR EQUAL (BXlE)
A successful-branching event also occurs
whenever one of the following
instructions is completed: PROGRAM CALL (PC) PROGRAM TRANSFER (PT) A successful-branching event causes a PER successful-branching event to be
recognized if bit 0 of the PER-event masks is one and the PER mask in the EC-mode PSW is one.
A PER successful-branching event is indicated by setting bit 0 of the PER code to one.
Instruction Fetching
An instruction-fetching event occurs if
the first byte of the instruction is
fetched from the storage area designated
by control registers 10 and 11. An
instruction-fetching event also occurs
if the first byte of the target of EXECUTE is within the designated storage
area. An instruction-fetching event causes a , PER i nstructi on-fetchi ng event to be
recognized if bit 1 of the PER-event masks;s one and the PER mask in the EC-mode PSW is one.
The PER instruction-fetching event is
indicated by setting bit 1 of the PER code to one.
Storage Alteration
A storage-alteration event occurs when­
ever a CPU, by using a logical or virtu­
al address, makes a store access without an access exception to the storage area designated by control registers 10 and 11 .
The contents of storage are considered
to have been altered whenever the CPU executes an instruction that causes all
or part of an operand or a DAS-trace
value to be stored within thQ designated storage area. Alteration is considered to take place whenever storing is
considered to take place for purposes of
indicating protection exceptions, except that recognition does not occur for the
storing of data by a channel program.
(See the section "Recognition of Access Exceptions" in Chapter 6, "Interrup­ tions.") Storing constitutes alteration
for PER purposes even if the value
stored is the same as the original
value.
Implied locations that are referred to
by the CPU in the process of
(1) interval-timer updating,
(2) interruptions, and (3) execution of I/O instructions are not monitored.
Such locations include the interval­
timer, old-PSW, interruption-code, and CSW locations. These locations,
however, are monitored when information
is stored there explicitly by an instruction. Similarly, monitoring does
not apply to the storing of data by a
channel program.
When an interruptible vector instruction
which performs storing is interrupted,
and PER storage alteration applies to
storage locations corresponding to
elements due to be changed beyond the
point of interruption, PER storage
alteration is indicated if any such
store actually occurred and may be indi­
cated even if such a store did not
occur. PER storage alteration is
reported for such locations only if no
access exception exists at the time that
the instruction is executed.
Storage alteration does not apply to
instructions whose operands are speci­
fied to be real addresses. Thus, stor­ age alteration does not apply to
INVALIDATE PAGE TABLE ENTRY, RESET REFERENCE BIT, RESET REFERENCE BIT
EXTENDED, SET STORAGE KEY, SET STORAGE KEY EXTENDED, and TEST BLOCK. When
INVALIDATE PAGE TABLE ENTRY is Chapter 4. Control 4-19

installed, the operand address of READ DIRECT is a real address and storage
alteration does not apply. When INVALI­
DATE PAGE TABLE ENTRY is not installed,
the operand address of READ DIRECT is a
logical address, and storage alteration
does apply.
A storage-alteration event causes a PER storage-alteration event to be recog­ nized if bit 2 of the PER-event masks is one and the PER mask in the EC-mode PSW 1 S one.
A PER storage-alteration event is indi­ cated by setting bit 2 of the PER code
to one.
General-Register Alteration
A general-register-alteration event
occurs whenever the contents of a gener­
al register are replaced. The contents of a general register are considered to have been altered whenever
a new value is placed in the register.
Recognition of the event is not contin­
gent on the new value being different
from the previous one. The execution of
an RR-format arithmetic, logical, or
movement instruction is considered to
fetch the contents of the register,
perform the indicated operation, if any,
and then replace the value in the regis­
ter. A register can be designated by an
RR, RRE, RS, or RX instruction or implicitly, such as in TRANSLATE AND
TEST and EDIT AND MARK.
The instructions MOVE LONG and COMPARE LOGICAL LONG are always considered to
alter the contents of the four registers specifying the two operands, including
the cases where the padding byte is
used, when both operands have zero
length. However, when condition code 3 is set for MOVE LONG, the general regis­
ters containing the operand lengths may
or may not be considered as having been
altered.
The instruction INSERT CHARACTERS UNDER
MASK is not considered to alter the
general register when the mask is zero.
The instructions COMPARE AND SWAP and COMPARE DOUBLE AND SWAP are considered
to alter the general register, or
general-register pair, designated by R
t
,
only when the contents are actually
replaced, that is, when the first and
second operands are not equal.
It is unpredictable whether general­
register-alteration events are indicated
for instructions of the vector facility.
A general-register-alteration event
causes a PER general-register-alteration
event to be recognized if bit 3 of the 4-20 System/370 Principles of Operation PER-event masks is one, the PER mask in
the EC-mode PSW is one, and the corre­
sponding bit in the PER general-register
mask is one.
The PER general-register-alteration
event is indicated by setting bit 3 of
the PER code to one. Programming Note
The following are some examples of
general-register alteration:
1. Register-to-register load instruc­
tions are considered to alter the
register contents even when both
operand addresses designate the
same register.
2. Addition or subtraction of zero and
multiplication or division by one
are considered to constitute alter­
ation.
3. Logical and fixed-point shift oper­
ations are considered to alter the
register contents even for shift
amounts of zero.
4. The branching instructions BRANCH ON INDEX HIGH and BRANCH ON INDEX LOW OR EQUAL are considered to
alter the first operand even when zero is added to its value. INDICATION OF PER EVENTS CONCURRENTLY WITH OTHER INTERRUPTION CONDITIONS The following rules govern the indi­
cation of PER events caused by an
instruction that also causes a program
exception, a monitor event, a space­
switch event, or a supervisor-call
interruption.
1. The indication of an instruction­ fetching event does not depend on
whether the execution of the
instruction was completed, termi­
nated, suppressed, or nullified.
The event, however, is not indi­
cated when an access exception
prohibits access to the first half­
word of the instruction. When the
first halfword of the instruction
is accessible but an access excep­
tion applies to the second or third
halfword of the instruction, it is unpredictable whether the
instruction-fetching event is indi­
cated. Similarly, when an access
exception prohibits access to all
or a portion of the target of EXECUTE, it is unpredictable wheth- er the instruction-fetching events , for EXECUTE and the target are
indicated.