For special-purpose instructions that
are not described in this publication, the operation of PER may not be exactly
as described in this section.
Identification of Cause A program interruption for PER sets bit
8 of the interruption code to one and
places identifying information in real
storage locations 150-155. The informa­
tion stored has the following format:
Locations 150-151: IPERClooooooooooool o 4 15
Locations 152-155: 1000000001 PER Address
o 8 31 PER Code (PERC): The occurrence of PER events is indicated by ones in bit posi­
tions 0-3 of real location 150, the PER code. The bit position in the PER code
for a particular type of event is the same as the bit position for that event
in the PER-evant-mask field in control
register 9. When a program interruption
occurs, more than one type of PER event
can be concurrently indicated. Addi­ tionally, if another program­
interruption condition exists, the
interruption code for the program inter­
ruption may indicate both the PER events
and the other condition. Zeros are
stored in bit positions 4-7 of location 150 and in bit positions 0-7 of location
151. PER Address: The PER address at
locations 152-155 contains the instruc­
tion address used to fetch the instruc­
tion in execution when one or more PER events were recognized. When the
instruction is the target of EXECUTE, the instruction address used to fetch
the EXECUTE instruction is placed in the PER-address field. Zeros are stored in the byte at real location 152.
Instruction Address: The instruction
address in the program old PSW is the
address of the instruction which would
have been executed next, unless another
program condition is also indicated, in which case the instruction address is that determined by the instruction
ending due to that condition.
) ILC: the
The ILC indicates the length
instruction designated by the
of PER address, except when a concurrent spec­
ification exception for the PSW intro­
duced by LOAD PSW or a supervisor-call
interruption sets an ILC of O. When a PER event is recognized during execution of a LOAD PSW or SUPERVISOR CALL instruction which changes CPU oper­
ation from the EC mode to the BC mode,
the interruption occurs with the old PSW specifying the BC mode and with the
interruption code stored in the old PSW. The additional information identifying
the PER event is stored in its regular
format at real locations 150-155. Priority of Indication
When a program interruption occurs and
more than one PER event has been recog­ nized, all recognized PER events are
concurrently indicated in the PER code.
Additionally, if another program­
interruption condition concurrently exists, the interruption code for the
program interruption indicates both the PER condition and the other condition.
In the case of an instruction-fetching
event for SUPERVISOR CALL, the program
interruption occurs immediately after
the supervisor-call interruption.
If a PER event is recognized during the
execution of an instruction which also
introduces a new PSW with the type of PSW-format error which is recognized
early (see the section "Exceptions Asso­ ciated with the PSW" in Chapter 6,
"Interruptions"), both the specification
exception and PER are indicated concur­
rently in the interruption code of the
program interruption. However, for a PSW-format error of the type which is
recognized late, only PER is indicated
in the interruption code. In both
cases, the invalid PSW is stored as the
program old PSW. Recognition of a PER event does not
normally affect the ending of instruc­
tion execution. However, in the follow­
ing cases, execution of an interruptible
instruction is not completed normally: When the instruction is due to be
interrupted for an asynchronous
condition (I/O, external, restart,
or repressible machine-check condi­
tion), a program interruption for
the PER event occurs first, and the
other interruptions occur subse­
quently (subject to the mask bits in
the new PSW) in the normal priority
order. When the stop function is performed,
a program interruption indicating
the PER event occurs before the CPU enters the stopped state. Chapter 4. Control 4-17
When any program exception is recog­
nized, PER events recognized for
that instruction execution are indi­
cated concurrently.
Depending on the model, in certain
situations, recognition of a PER event may appear to cause the
instruction to be interrupted prema­
turely without concurrent indication
of a program exception, without an
interruption for any asynchronous
condition, or without the CPU enter­
ing the stopped state. Programming Notes 1. In the following cases, an instruc­
tion can both cause a program
interruption for a PER event and change the value of masks control­
ling an interruption for PER events. The original mask values
determine whether a program inter­
ruption takes place for the PER event.
a. The instructions LOAD PSW, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and SUPERVISOR CALL can cause an instruction­
fetching event and disable the CPU for PER interruptions.
Additionally, STORE THEN AND SYSTEM MASK can cause a storage-alteration event to be indicated. In all these cases,
the program old PSW associated
with the program interruption
for the PER event may indicate
that the CPU was disabled for PER events.
b. An instruction-fetching event
may be recognized during
execution of a LOAD CONTROL
instruction that changes the
value of the PER-event masks in
control register 9 or the
addresses in control registers 10 and 11 controlling indi­ cation of instruction-fetching
events.
2. No instruction can both change the
values of general-register-altera­
tion masks and cause a general­
register-alteration event to be
recognized.
3. When a PER interruption occurs
during the execution of an inter­
ruptible instruction, the ILC indi­
cates the length of that
instruction or EXECUTE, as appro­
priate. When a PER interruption
occurs as a result of LOAD PSW or
4-18 System/370 Principles of Operation SUPERVISOR CALL, the ILC indicates
the length of these instructions or
EXECUTE, as appropriate, unless a
concurrent specification exception
on LOAD PSW calls for an ILC of O. 4. When a PER interruption is caused
by branching, the PER address iden­
tifies the branch instruction (or
EXECUTE, as appropriate), whereas
the old PSW points to the next
instruction to be executed. When
the interruption occurs during the
execution of an interruptible
instruction, the PER address and
the instruction address in the old PSW are the same.
STORAGE-AREA DESIGNATION Two types of PER events --instruction
fetching and storage alteration-­
involve the designation of an area in
storage. The storage area starts at the
location designated by the starting
address in control register 10 and
extends up to and including the location
designated by the ending address in
control register 11. The area extends
to the right of the starting address.
An instruction-fetching event occurs
whenever the first byte of an instruc­
tion or the first byte of the target of
an EXECUTE instruction is fetched from
the designated area. A storage­
alteration event occurs when a store
access is made to the designated area by
using an operand address that is defined
to be a logical or a virtual address. A
storage-alteration event does not occur
for a store access made with an operand
address defined to be a real address.
The set of addresses designated for
instruction-fetching and storage­
alteration events wraps around at address 16,777,215; that is, address 0 is considered to follow address
16,777,215. When the starting address
is less than the ending address, the
area is contiguous. When the starting
address is greater than the ending
address, the set of locations designated
includes the area from the starting
address to address 16,777,215 and the
area from address 0 to, and including,
the ending address. When the starting
address is equal to the ending address,
only that one location is designated.
Address comparison for instruction­
fetching and storage-alteration events
is performed by comparing all 24 bits of
the virtual, logical or instruction
address used for the reference with the
starting and ending addresses.
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