For special-purpose instructions that
are not described inthis publication, the operation of PER may not be exactly
as described in this section.
Identification ofCause A program interruption for PER sets bit
8 of the interruption code to one and
placesidentifying information in real
storage locations150-155. The informa
tion stored has the following format:
Locations150-151: IPERClooooooooooool o 4 15
Locations 152-155:1000000001 PER Address
o 8 31PER Code (PERC): The occurrence of PER events is indicated by ones in bit posi
tions0-3 of real location 150, the PER code. The bit position in the PER code
for a particular type of eventis the same as the bit position for that event
in thePER-evant-mask field in control
register 9. Whena program interruption
occurs, more than one type ofPER event
can be concurrently indicated.Addi tionally, if another program
interruption condition exists, the
interruption code for the program inter
ruption mayindicate both the PER events
andthe other condition. Zeros are
stored in bit positions 4-7 of location150 and in bit positions 0-7 of location
151.PER Address: The PER address at
locations 152-155 contains the instruc
tion address used to fetch the instruc
tion in execution when one or morePER events were recognized. When the
instructionis the target of EXECUTE, the instruction address used to fetch
theEXECUTE instruction is placed in the PER-address field. Zeros are stored in the byte at real location 152.
Instruction Address: The instruction
address in the program oldPSW is the
address of the instruction which would
have been executed next, unless another
program condition is alsoindicated, in which case the instruction address is that determined by the instruction
ending due to that condition.
)ILC: the
TheILC indicates the length
instruction designated by the
ofPER address, except when a concurrent spec
ification exception for thePSW intro
duced by LOADPSW or a supervisor-call
interruption sets anILC of O. When a PER event is recognized during execution of a LOAD PSW or SUPERVISOR CALL instruction which changes CPU oper
ation from theEC mode to the BC mode,
the interruption occurswith the old PSW specifying the BC mode and with the
interruption code storedin the old PSW. The additional information identifying
thePER event is stored in its regular
format at real locations150-155. Priority of Indication
When a program interruption occurs and
more than onePER event has been recog nized, all recognized PER events are
concurrently indicated in thePER code.
Additionally, if another program
interruption condition concurrentlyexists, the interruption code for the
program interruption indicates both thePER condition and the other condition.
In the case of an instruction-fetching
event forSUPERVISOR CALL, the program
interruption occurs immediately after
the supervisor-call interruption.
If aPER event is recognized during the
execution of an instruction which also
introducesa new PSW with the type of PSW-format error which is recognized
early(see the section "Exceptions Asso ciated with the PSW" in Chapter 6,
"Interruptions"), both the specification
exception andPER are indicated concur
rently in the interruption code of the
program interruption. However, for aPSW-format error of the type which is
recognized late, onlyPER is indicated
in the interruption code. In both
cases, the invalidPSW is stored as the
program oldPSW. Recognition of a PER event does not
normally affect the ending of instruc
tion execution. However, in the follow
ing cases, execution of an interruptible
instruction is not completed normally:• When the instruction is due to be
interrupted for an asynchronous
condition (I/O, external, restart,
or repressible machine-check condi
tion),a program interruption for
thePER event occurs first, and the
other interruptions occur subse
quently (subject to the mask bits in
the newPSW) in the normal priority
order.• When the stop function is performed,
a program interruption indicating
thePER event occurs before the CPU enters the stopped state. Chapter 4. Control 4-17
are not described in
as described in this section.
Identification of
8 of the interruption code to one and
places
storage locations
tion stored has the following format:
Locations
Locations 152-155:
o 8 31
tions
for a particular type of event
in the
register 9. When
occurs, more than one type of
can be concurrently indicated.
interruption condition exists, the
interruption code for the program inter
ruption may
and
stored in bit positions 4-7 of location
151.
locations 152-155 contains the instruc
tion address used to fetch the instruc
tion in execution when one or more
instruction
the
Instruction Address: The instruction
address in the program old
address of the instruction which would
have been executed next, unless another
program condition is also
ending due to that condition.
)
The
instruction designated by the
of
ification exception for the
duced by LOAD
interruption sets an
ation from the
the interruption occurs
interruption code stored
the
format at real locations
When a program interruption occurs and
more than one
concurrently indicated in the
Additionally, if another program
interruption condition concurrently
program interruption indicates both the
In the case of an instruction-fetching
event for
interruption occurs immediately after
the supervisor-call interruption.
If a
execution of an instruction which also
introduces
early
"Interruptions"), both the specification
exception and
rently in the interruption code of the
program interruption. However, for a
recognized late, only
in the interruption code. In both
cases, the invalid
program old
normally affect the ending of instruc
tion execution. However, in the follow
ing cases, execution of an interruptible
instruction is not completed normally:
interrupted for an asynchronous
condition (I/O, external, restart,
or repressible machine-check condi
tion),
the
other interruptions occur subse
quently (subject to the mask bits in
the new
order.
a program interruption indicating
the