Explanation (Continued): RA I/O-system reset is performed in all the channels in the configuration and
pending I/O-interruption conditions are cleared. As part of this reset,
system reset is signaled to the I/O control units and devices attached to
the channels being reset. RC I/O-system reset is performed in those channels connected to the CPU per­
forming the program reset or initial-program reset. As part of this reset,
system reset is signaled to the I/O control units and devices attached to
the channels being reset. S The CPU is reset; current operations, if any, are terminated; the TlB is
cleared of entries; interruption conditions in the CPU are cleared; and the CPU ;s placed in the stopped state. The effect of performing the start
function is unpredictable when the stopped state has been entered by means
of a reset.
T The TOD clock is initialized to zero and validated; it enters the not-set
state. U The state, condition, or contents of the field remain unchanged. However,
the result is unpredictable if an operation is in progress that changes the
state, condition, or contents of the field at the time of reset. U/V The contents remain unchanged, provided the field is not being changed at
the time the reset function is performed. However, on some models, the
checking-block code of the contents may be made valid. The result is un­
predictable if an operation is in progress that changes the contents of the
field at the time of reset.
Summary of Reset Actions (Part 2 of 2) CPU reset causes the following actions:
1. The execution of the current
instruction or other processing
sequence, such as an interruption,
is terminated, and all program­
interruption and supervisor-call­
interruption conditions are
cleared.
2. Any pending external-interruption
conditions which are local to the CPU are cleared. Floating
external-interruption conditions
are not cleared.
3. Any pending machine-cheek-interrup­
tion conditions and error indi­
cations which are local to the CPU and any check-stop states are
cleared. Floating machine-check­
interruption conditions are not
cleared. Any machine-check condi­
tion which is reported to all CPUs in the configuration and which has
been made pending to a CPU is said
to be local to the CPU. 4. All copies of prefetched
instructions or operands are cleared. Additionally, any results
to be stored because of the
execution of instructions in the
current checkpoint interval are
cleared.
5. The translation-lookaside buffer is
cleared of entries.
6. The CPU is placed in the stopped
state after actions 1-5 have been
completed. When the IPl sequence
follows the reset function on that CPU, the CPU enters the load state
at the completion of the reset
function and does not necessarily enter the stopped state during the
execution of the reset operation.
Registers, storage contents, and the
state of conditions external to the CPU remain unchanged by CPU reset. However,
the subsequent contents of the register,
location, or state are unpredictable if
an operation is in progress that changes
the contents at the time of the reset.
When the reset function in the CPU is
initiated at the time the CPU is execut­
ing an I/O instruction or is performing
an I/O interruption, the current opera­
tion between the CPU and the channel may
or may not be completed, and the result­
ant state of the associated channel may
be unpredictable. Programming Note
Most operations which would change a
state, a condition, or the contents of a Chapter 4. Control 4-33
field cannot occur when the CPU is in the stopped state. However, some
signal-processor functions and some
operator functions may change these
fields. To eliminate the possibility of
losing a field when CPU reset is issued,
the CPU should be stopped, and no opera­
tor functions should be in progress.
Initial CPU Reset
Initial CPU reset combines the CPU reset
functions with the following clearing
and initializing functions:
1. The contents of the current PSW, prefix, CPU timer, and clock compa­
rator are set to zero. When the IPl sequence follows the reset
function on that CPU, the contents
of the PSW are not necessarily set
to zero.
2. All assigned control-register posi­
tions are set to their initial
value.
These clearing and initializing func­
tions include validation.
Setting the current PSW to zero causes
the PSW to assume the BC-mode format. The instruction-length code and inter­
ruption code are unpredictable, because
these values are not retained when a new PSW is introduced.
Subsystem Reset
Subsystem reset operates only on those
elements in the configuration which are not CPUs. It performs the following
actions:
1. I/O-system reset is performed in each channel in the configuration.
2.
3.
All floating
tions in the
cleared.
interruption condi­ configuration are
Channel-set connections initialized to connect each
set to its home CPU if one is operational, and is
configuration, or else to
channel set disconnected.
are
channel
exists,
in the
make the
As part of I/O-system reset, pending
I/O-interruption conditions are cleared,
and system reset is signaled to all
control units and devices attached to
the channel (see the section "I/O-System Reset" in Chupter 13, "Input/Output Operations"). The effect of system reset on I/O control units and devices
and the control-unit and device state are described in the appro-
4-34 System/370 Principles of Operation priate System library publication for
the control unit or device. A system
reset, in general, resets only those
functions in a shared control unit or
device that are associated with the
particular channel signaling the reset. Program Reset
For program reset, CPU reset is
performed, and I/O-system reset is performed in each channel connected to this CPU. Initial Program Reset
Initial program reset combines the
program-reset functions with the clear­
ing and initializing functions of
initial CPU reset. Clear reset combines
reset function with
function which causes
actions:
the initial-CPU­ an initializing
the following
1. In most models, the contents of the
general and floating-point regis­
ters of those CPUs which are in the
configuration are set to zero, but in some models the contents may be
left unchanged except that the
checking-block code is made valid.
2. The registers (vector-status regis­
ter, vector-mask register, vector­
activity count, and all vector
registers) of those vector facili­
ties, if any, which are in the
configuration are cleared to zero
with valid checking-block code.
3. The contents of the main storage in the configuration and the associ­
ated storage keys are set to zero
with valid checking-block code.
4. A subsystem reset is performed.
Validation is included in setting regis­
ters and in clearing storage and storage
keys.
Programming Notes
1. For the CPU-reset or program-reset
operation not to affect the
contents of fields that are to be
left unchanged, the CPU must not be
executing instructions and must be
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