disabled for all interruptions at
the time of the reset. Except for
the operation of the interval timer
and CPU timer and for the possibil­
ity of a machine-check interruption
occurring, all CPU activity can be stopped by placing the CPU in the
wait state and by disabling it for I/O and external interruptions. To
avoid the possibility of causing a reset at the time that the interval
timer or CPU timer is being updated
or a machine-check interruption
occurs, the CPU must be in the stopped state.
2. CPU reset, initial CPU reset,
subsystem reset, program reset,
initial program reset, and clear
reset do not affect the value and
state of the TOO clock.
3. The conditions under which the CPU enters the check-stop state are model-dependent and include
malfunctions that preclude the
completion of the current
operation. Hence, if CPU reset,
initial CPU reset, program reset, or initial program reset is
executed while the CPU is in the
check-stop state, the contents of
the PSW, registers, and storage
locations, including the storage
keys and the storage location
accessed at the time of the error, may have unpredictable values, and,
in some ca5es, the contents may still be in error after the check­
stop state is cleared by these resets. In this situation, a clear
reset is required to clear the
error.
4. Clear reset causes all bit posi­
tions of the interval timer to be
cleared to zeros. Power-On Reset
The power-on-reset function for a compo­
nent of the machine is performed as part
of the power-on sequence for that compo­
nent.
The power-on sequences for the TOO clock, vector facility, main storage, expanded storage, and channels may be included as part of the CPU power-on scquence, or the power-on sequence for these units may be initiated separately.
The following sections describe the
power-on resets for the CPU, TOD clock,
vector facility, main storage, expanded storage, and channels. See also Chapter 13, "Input/Output Operations," and the
appropriate System Library publication for channels, control units, and I/O devices. CPU Power-On Reset: The power-on reset causes initial CPU reset to be performed
and mayor may not cause I/O-system reset to be performed in the channels
connected to the CPU. The contents of
general registers and floating-point
registers normally are cleared to zeros, but in some models may be left unpre­
dictable, with valid checking-block
code. TOO-Clock Power-On Reset: The power-on reset causes the the TOO clock
to be set to zero and causes the clock
to enter the not-set state.
Vector-Facility Power-On Reset: The
power-on reset causes the registers of the vector facility (vector-status
register, vector-mask register, vector­
activity count, and all vector
registers) to be cleared to zeros with
valid checking-block code.
Main-Storage Power-On Reset: For vola­
tile main storage (one that does not
preserve its contents when power is off)
and for storage keys, power-on reset
causes valid checking-block code to be placed in these fields. In most models, the contents are cleared to zeros, but,
in some models, the contents may be left
unpredictable except for the checking­
block code. The contents of nonvolatile
main storage, including the checking­
block code, remain unchanged.
Expanded-Storage Power-On Reset: The
contents of the expanded storage are cleared to zeros with valid checking­
block code. Channel Power-On Reset: The channel pOL.Jer-on reset causes I/O-system reset
to be performed. (See the section "I/O-System Reset" in Chapter 13,
"Input/Output Operations.")
INITIAL PROGRAM LOADING Initial program loading (IPL) provides a manual means for causing a program to be read from a designated device and for
initiating execution of that program.
Some models may provide additional
controls and lndications relating to IPl; this additional information is
specified in the System library publica­
tion for the model. IPL is initiated manually by setting the
load-unit-address controls to designate
an input device and by subsequently
activating the load-clear or load-normal
key for a particular CPU. In the description which follows, the term "this CPU" refers to the CPU in the
configuration for which the load-clear
or load-normal key was activated. Chapter 4. Control 4-35

Activating the load-clear key causes a
clear reset to be performed on the
configuration.
Activating the load-normal key causes an
initial CPU reset to be performed on
this CPU, CPU reset to be propagated to
all other CPUs in the configuration, and
a sUbsystem reset to be performed on the
remainder of the configuration.
In the loading part of the operation,
after the resets have been performed,
this CPU then enters the load state.
This CPU does not necessarily enter the
stopped state during the execution of
the reset operations. The load indica­
tor is on while the CPU is in the load
state.
Subsequently, a channel program read
operation is initiated from the channel
and I/O device designated by the load­
unit-address controls.
The read operation is performed as if a
START I/O instruction were executed that
specified the channel, subchannel, and I/O device designated by the load-unit­
address controls. The operation uses an
implied channel-address word (CAW) containing a subchannel key of zero, a
suspend-control bit of zero, and a channel-command-word (CCW) address of 0, but the CAW at real location 72 is not
accessed. The load-unit-address
controls provide the 16-bit I/O address,
of which the leftmost eight bits are the channel address and the rightmost eight bits the device address; any leftmost
bits of the channel address that are
omitted because they are not needed to
select a channel are implied to be
zeros.
Although the absolute location of the
first CCW to be executed is specified by the CCWaddress as 0, the first CCW actually executed is an implied CCW, containing, in effect, a read command
with the modifier bits set to zeros, a
data address of 0, a byte count of 24,
the chain-command and SLI flags set to
ones, and the chain-data, skip,
indirect-data-address, suspend, and PCI flags set to zeros. The CCW fetched, as a result of command chaining, from abso­
lute location 8 or 16, as well as any
subsequent CCW in the IPL sequence, is
interpreted the same as a CCW in any I/O operation, except that any PCI flags
that are specified in CCWs used in the IPL channel program are ignored.
When the I/O device provides channel-end
status for the last operation of the IPL channel program and no exceptional
conditions are detected in the
operation, a new PSW is loaded from
absolute storage locations 0-7. When
this PSW specifies the EC mode, the I/O address that was used for the IPL opera­
tion is stored at absolute locations
186-187, and zeros are stored at abso-
4-36 System/370 Principles of Operation lute location 185; when the BC mode is
specified, the I/O address is stored at
absolute locations 2-3. If the PSW loading is successful and if no machine
malfunctions are detected, this CPU leaves the load state and the load indi­
cator is turned off. If the rate
control is set to the process position,
the CPU enters the operating state and
the CPU operation proceeds under control
of the new PSW. If the rate control is
set to the instruction-step position,
the CPU enters the stopped state, with
the manual indicator on, after the new PSW is loaded.
When channel-end status for the last CCW of the IPL channel program is presented,
either separate from or along with device-end status, no I/O-interruption
condition is generated. Similarly, any PCI flags specified by the program in
the CCWs used for the IPL sequence are
ignored. If the device-end status for
the IPL operation is provided separately
after channel-end status, it causes an I/O interruption condition to be gener­
ated.
If the IPL I/O operation or the PSW loading is not completed successfully,
the CPU remains in the load state, and
the load indicator remains on. This
occurs when the device designated by the
load-unit-address controls is not opera­
tional, when the device or channel
signals any condition other than channel
end, device end, or status modifier
during or at the completion of the last CCW of the IPL channel program, or when
the PSW loaded from absolute location 0 has a PSW-format error of the type that
is recognized early. The address of the I/O device used in the IPL operation is
not stored. The contents of absolute
storage locations 0-7 are unpredictable.
The contents of other storage locations
remain unchanged, except possibly for
those locations due to be changed by the read operations.
When fewer than eight bytes are
into absolute locations 0-7, the
fetched from absolute location 0 at
conclusion of the IPl operation
unpredictable. Programming Notes
read PSW the
is
1. The information read and placed at
absolute locations 8-15 and 16-23
may be used as CCWs for reading additional information during the IPL I/O operation: the CCW at
absolute location 8 may specify
reading additional CCWs elsewhere
in storage, and the CCW at absolute
location 16 may specify the
transfer-in-channel command, caus­
ing transfer to these CCWs.