Condition Control-register-O contents
l
Invalid encoding of bits 8-12 Segment-table entry
Segment-table-length violation
Entry protected against fetching
Invalid address of entry
I bit on One in a bit position which is
checked for zer0
3 Page-table entry Page-table-length violation
Entry protected against fetching
Invalid address of entry
I bit on One in a bit position which is
checked for zer0
3 Access for instruction fetch
Location protected
Invalid address
Access for operands
Location protected
Invalid address
Explanation:
Translation for
Virtual Address
of LRA
Indi­
cation TS cc3
A
eel TS cc3
A
cc2 TS Action Suppress Complete Suppress Complete Suppress Complete Suppress Complete Suppress The condition does not apply. Translation and Access for
Logical Address
of TPROT Indi­
cation
cc3
A
cc3 TS cc3
A
cc3 TS Action Complete Suppress Complete Suppress Complete Suppress Complete Suppress cc set
4 Complete A Suppress Translation and
Access for Any Other Address
Indi­
cation TS ST A ST TS PT
A PT TS P
A
P
A
Action Suppress Nullify Suppress Nullify Suppress Nullify Suppress Nullify Suppress Suppress Suppress Term.* Term.* * 1
Action is to terminate except where otherwise specified in this publication.
A translution-specification exception for an invalid code in control reg­ ister 0, bit positions 8-12, is recognized as part of the execution of the
instruction using address translation; when DAT is on, it is recognized during translation of the instruction address, and, when DAT is off, it is
only recognized during execution of INVALIDATE PAGE TABLE ENTRY or for
translation of the operand address of LOAD REAL ADDRESS. 2 3 4 A
eel
cc2
cc3
P
PT ST TS A translation-specification exception cannot occur for the logical address
of TEST PROTECTION because this exception would have been recognized during
the instruction fetch for the instruction.
A translation-specification exception for a format error in a table entry
is recognized only when the execution of an instruction requires the entry
for trunslation of an address.
The condition code is set as follows:
o Operand location not protected.
1 Fetches permitted, but stores not 2 Neither fetches nor stores permitted. Addressing exception. Condition code I set. Condition codQ 2 set. Condition code 3 set.
Protection exception.
Page-translation exception. Segment-translation exception.
Translation-specification exception.
Handling of Access Exceptions Chapter 6. Interruptions 6-29

Any access exception is recognized as
part of the execution of the instruction
with which the exception is associated.
An access exception is not recognized
when the CPU attempts to prefetch from
an unavailable location or detects some
other access-exception condition, but a
branch instruction or an interruption
changes the instruction sequence such that the instruction is not executed.
Every instruction can cause an access
exception to be recognized because of
instruction fetch. Additionally, access
exceptions associated with instruction
execution may occur because of an access
to an operand in storage.
An access exception due to fetching an
instruction is indicated when the first
instruction halfword cannot be fetched without encountering the exception.
When the first halfword of the instruc­ tion has no access exceptions, access exceptions may be indicated for addi­
tional halfwords according to the instruction length specified by the
first two bits of the instruction;
however, when the operation can be
performed without accessing the second
or third halfwords of the instruction,
it is unpredictable whether the access exception is indicated for the unused
part. Since the indication of access exceptions for instruction fetch is common to all instructions, it is not
covered in the individual instruction
definitions.
Except where otherwise indicated in the
individual instruction description, the
following rules apply for exceptions associated with an access to an operand
location. For a fetch-type operand,
access exceptions are necessarily indi­ cated only for that portion of the
operand which is required for completing
the operation. It is unpredictable
whether access exceptions are indicated
for those portions of a fetch-type oper­ and which are not required for
completing the operation. For a store­
type operand, access exceptions are
recognized for the entire operand even if the operation could be completed
without the use of the inaccessible part of the operand. In situations where the
value of a store-type operand is defined
to be unpredictable, it is unpredictable
whether an access exception is indicated.
Whenever an access to an operand
location can cause an access exception
to be recognized, the word "access" is included in the list of program
exceptions in the description of the
instruction. This entry also indicates
which operand can cause the exception to
be recognized and whether the exception
is recognized on a fetch or store access
to that operand location. Access
exceptions are recognized only for the 6-30 System/370 Principles of Operation
portion of the operand as defined by
each particular instruction. MULTIPLE PROGRAM-INTERRUPTION CONDITIONS Except for PER events, only one
program-interruption condition is indi­
cated with a program interruption. The
existence of one condition, however, does not preclude the existence of other
conditions. When more than one
program-interruption condition exists, only the condition having the highest
priority is identified in the inter­
ruption code.
With two conditions of the same priority, it is unpredictable which is indicated. In particular, the priority
of access exceptions associated with the
two parts of an operand that crosses a page or protection boundary is unpre­
dictable and is not necessarily related
to the sequence specified for the access
of bytes within the operand.
The type of ending which occurs (nulli­
fication, suppression, or termination) is that which is defined for the type of
exception that is indicated in the
interruption code. However, if a condi­ tion is indicated which permits
termination, and another condition also
exists which would cause either nullifi­
cation or suppression, then the unit of
operation is suppressed. The figure "Priority of Program­
Interruption Conditions" lists the
priorities of all program-interruption
conditions other than PER events and
exceptions associated with DAS. All
exceptions associated with references to storage for a particular instruction
halfword or a particular operand byte
are grouped as a single entry called
"access." The figure "Priority of
Access Exceptions" lists the priority of
access exceptions for a single access.
Thus, the second figure specifies which
of several exceptions, encountered
either in the access of a particular
portion of an instruction or in any particular access associated with an
operand, has highest priority, and the first figure specifies the priority of
this condition in relation to other
conditions detected in the operation. Similarly, the priorities for exceptions
occurring as part of ASH translation and
tracing are covered in the figures "Pri­ ority of ASH-Translation Exceptions" and
"Priority of Trace Exceptions," respec­
tively.
For some instructions, the shown in the individual
description.
priority is instruction
The relative priorities of any two
conditions listed in the figure can be