Explanation:
Numbers indicate
no priority.
23 4
5
6
7PSW errors which cause an immediate interruption may be introduced by a new PSW loaded as a result of an interruption or by the instructions LOAD SYSTEM MASK, and STORE THEN OR SYSTEM MASK. The priority shown in the
chart is for aPSW error introduced by an interruption and may also be con
sidered as the priority fora PSW error introduced by the previous instruc
tion. The error is introduced only if the instruction encounters no other
exceptions. The resulting interruption has a higher priority than any inter
ruption caused by the instruction which would have been executed next; it has
lower priority, however, than any interruption caused by the instruction which
introduced the erroneousPSW. Priorities EXECUTE instruction, and priorities start
ing with 6 are for the target instruction. When noEXECUTE is
Separate accesses may occur for each halfword of an instruction. The second
instruction halfword is accessed only if bits0-1 of the instruction are not
both zeros. The third instruction halfword is accessed only if bits0-1 of
of the instruction are both ones. Access exceptions for one of these half
words are not necessarily recognized if the instruction can be completed
without use ofthe contents of the halfword or if an exception of lower pri
ority can be determined without the use of the halfword.
As in instruction fetching, separate accesses may occur for each portion of
an operand. Each of these accesses is of equal priority, and the two entries
8.B and8.C are listed to represent the relative priorities of exceptions as-
sociated with any two of these accesses. Access exceptions forINSERT STORAGE KEY, INSERT STORAGE KEY EXTENDED, INSERT VIRTUAL STORAGE KEY, INVALI
DATE PAGE TABLEENTRY, LOAD REAL ADDRESS, RESET REFERENCE BIT, RESET REFERENCE BIT EXTENDED, SET STORAGE KEY, SET STORAGE KEY EXTENDED, and TEST PROTECTION are also included in 8.B.
ForMOVE LONG and COMPARE LOGICAL LONG, an access exception for a particular
operand canbe indicated only if the R field for that operand designates an
even-numbered register.
The exceptioncan be indicated only if the sign, digit, or digits responsi
ble for the exceptionwere fetched without encountering an access exception.
The exceptioncan be indicated only if the digits used in establishing the
exception, and also the signs, were fetched without encountering an access
exception, only if the signs are valid,and only if the digits used in estab
lishing the exceptionare valid.
Priority of Program-InterruptionConditions (Part 2 of 2)
Access Exceptions
The access exceptions consist of those
exceptions which canbe encountered while using an absolute, instruction,
logical, real, or virtual address toaccess storage. Thus, with DAT on, the
exceptionsare: 1. Translation specification
2. Segment translation
3.Page translation
4. Addressing
5. Protection (key-controlled,
ment, and low-address)
With DAT off, the exceptions are:
1. Addressing
2. Protection (key-controlled
low-address)
seg-
and
Additionally, the instructionsLOAD REAL
ADDRESS and INVALIDATEPAGE TABLE ENTRY can encounter a translation
specification exceptioneven with DAT
off.Chapter 6. Interruptions 6-33
Numbers indicate
no priority.
2
5
6
7
chart is for a
sidered as the priority for
tion. The error is introduced only if the instruction encounters no other
exceptions. The resulting interruption has a higher priority than any inter
ruption caused by the instruction which would have been executed next; it has
lower priority, however, than any interruption caused by the instruction which
introduced the erroneous
ing with 6 are for the target instruction. When no
Separate accesses may occur for each halfword of an instruction. The second
instruction halfword is accessed only if bits
both zeros. The third instruction halfword is accessed only if bits
of the instruction are both ones. Access exceptions for one of these half
words are not necessarily recognized if the instruction can be completed
without use of
ority can be determined without the use of the halfword.
As in instruction fetching, separate accesses may occur for each portion of
an operand. Each of these accesses is of equal priority, and the two entries
8.B and
sociated with any two of these accesses. Access exceptions for
DATE PAGE TABLE
For
operand can
even-numbered register.
The exception
ble for the exception
The exception
exception, and also the signs, were fetched without encountering an access
exception, only if the signs are valid,
lishing the exception
Priority of Program-Interruption
Access Exceptions
The access exceptions consist of those
exceptions which can
logical, real, or virtual address to
exceptions
2. Segment translation
3.
4. Addressing
5. Protection (key-controlled,
ment, and low-address)
With DAT off, the exceptions are:
1. Addressing
2. Protection (key-controlled
low-address)
seg-
and
Additionally, the instructions
ADDRESS and INVALIDATE
specification exception
off.
