The R, and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Condition Code: The
unchanged.
code remains
Program Exceptions:
Access (fetch,
LD only)
Operation (if
facility is
Specification
operand 2 of LE and
the floating-point
not installed) LOAD AND TEST
[RR, Short Operands]
'32'
o 8 12 15
[RR, Long Operands] , 22 ' I R
t I R 2 o 8 12 15
The second operand is placed unchanged
at the first-operand location, and its
sign and magnitude are tested to deter­
mine the setting of the condition code.
The R, and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Resulting Condition Code:
o
1
2 3 Result fraction zero
Result less than zero
Result greater than zero
Program Exceptions:
Operation (if the floating-point
facility is not installed)
Specification
Programming Note
When the same register is designated as
the first-operand and second-operand
location, the operation is equivalent to
a test without data movement. LOAD COMPLEMENT
[RR, Short Operands]
'33' 0 8 12 15
LCDR R, , R2 [RR, Long Operands]
'23' I R, I R2 0 8 12 15
The second operand is placed at the
first-operand location with the sign bit
inverted.
The sign bit is inverted, even if the
fraction is zero. The characteristic
and fraction are not changed.
The Rt and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Resulting Condition Code:
o Result fraction zero
1 Result less than zero
2 Result greater than zero
3
Program Exceptions:
Operation (if the floating-point
facility is not installed)
Specification LOAD NEGATIVE [RR, Short Operands]
o 8 12 15
[RR, Long Operands]
'21'
o 8 12 15
The second operand is
first-operand location
made minus.
placed at the
with the sign
The sign bit is made one, even if the
fraction is zero. The characteristic
and fraction are not changed.
The R, and R2 fields must designate
register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Chapter 9. Floating-Point Instructions 9-11

Resulting Condition Code: o Result fraction zero 1 Result less than zero 2
3 Program Exceptions: Operation (if the floating-point
facility is not installed)
Specification LOAD POSITIVE [RR, Short Operands] o 8 12 15
[RR, Long Operands] o 8 12 15 The second operand is
first-operand location made plus.
placed at the with the sign The sign bit is made zero. The charac­
teristic and fraction are not changed. The Rl and R2 fields must designate register 0, 2, 4, or 6; otherwise, a
specification exception is recognized.
Resulting Condition Code: o Result fraction zero 1
2 Result greater than zero 3 Program Exceptions: Operation (if the floating-point
facility is not installed)
Specification LOAD ROUNDED lRER Rt,R
2
[RR, long Operand 2, Short Operand 1]
o 8 12 15
9-12 System/370 Principles of Operation
LRDR R
1 ,R
2
o
[RR, Extended Operand 2,
long Operand 1]
'25' I Rl I R2 I 8 12 15 The second operand is rounded to the next shorter format, and the result is
placed at the first-operand location.
Rounding consists in adding a one in bit
position 32 or 72 of the long or
extended second operand, respectively, and propagating any carry to the left. The sign of the fraction is ignored, and
addition is performed as if the frac­
tions were positive.
If rounding causes a carry out of the
leftmost hexadecimal digit position of
the fraction, the fraction is shifted
right one digit position so that the
carry becomes the leftmost digit of the
fraction, and the characteristic is
increased by one. The intermediate fraction is then trun­ cated to the proper result-fraction
length.
The sign of the result is the same as the sign of the second operand. There is no normalization to eliminate leading
zeros.
An exponent-overflow exception exists when shifting the fraction right would cause the characteristic to exceed 127. The operation is completed by loading a
number whose characteristic is 128 less
than the correct value, and a program
interruption for exponent overflow
occurs. The result is normalized, and
the sign and fraction remain correct.
Exponent-underflow and
exceptions cannot occur.
significance The Rl field must designate register 0, 2, 4, or 6; the R2 field of lRER must
designate register 0, 2, 4, or 6; and the R2 field of lRDR must designate register 0 or 4. Otherwise, a specifi­
cation exception is recognized.
Condition Code: unchanged. Program Exceptions: The Exponent overflow code remains
Operation (if the extended-
precision floating-point facil­
ity is not installed)
Specification