SET CLOCK SCK [5] '8204' o 16 20 31
The current value of the TOO clock is replaced by the contents of the double­
word designated by the second-operand address, and the clock enters the
stopped state.
The doubleword operand replaces the
contents of the clock, as determined by
the resolution of the clock. Only those
bits of the operand are set in the clock
that correspond to the bit positions
which are updated by the clock; the
contents of the remaining rightmost bit
positions of the operand are ignored and
are not preserved in the clock. In some
models, starting at or to the right of
bit position 52, the rightmost bits of
the second operand are ignored, and the
corresponding positions of the clock
which are implemented are set to zeros.
After the clock value is set, the clock
enters the stopped state. The clock
leaves the stopped state to enter the
set state and resume incrementing under
control of the TOD-clock-sync control
(bit 2 of control register 0). When the
bit is zero or the TOD-clock- synchronization facility is not
installed, the clock enters the set
state at the completion of the instruc­
tion. When the bit is one, the clock
remains in the stopped state either
until the bit is set to zero or until
any other running TOO clock in the
configuration is incremented to a value
of all zeros in bit positions 32-63.
When the TOO clock is shared by another CPU, the clock remains in the stopped
state under control of the TOD-clock­
sync control bit of the CPU which set
the clock. If, while the clock is
stopped, it is set by another CPU, then
the clock comes under control of the
TOD-clock-sync control bit of the CPU which last set the clock.
The value of the clock is changed and
the clock is placed in the stopped state
only if the manual TOO-clock control of
any CPU in the configuration is set to
the enable-set position. If the TOD­ clock control is set to the secure
position, the value and the state of the
clock are not changed. The two results
are distinguished by condition codes 0 and 1, respectively.
When the clock is not operational, the
value and state of the clock are not
changed, regardless of the setting of
the TOO-clock control, and condition
code 3 is set. Special Conditjons The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized.
Resulting Condjtion Code: o Clock value set
1 Clock value secure
2
3 Clock in not-operational state Program Exceptions:
Access (fetch, operand 2) Privileged operation Specification Programming Note
In an installation with more than one CPU, each CPU may have a separate TOO clock, or more than one CPU may share a TOO clock, depending on the model. When
multiple TOO clocks exist, special
procedures are required to synchronize
the clocks. See the section "TOO-Clock Synchronization" in Chapter 4, "Control." SET CLOCK COMPARATOR SCKC [5] '8206' o 16 20 31
The current value of the clock compara­
tor is replaced by the contents of the
doubleword designated by the second­
operand address. Only those bits of the operand are set
in the clock comparator that correspond
to the bit positions to be compare.d with
the TOO clock; the contents of the
remaining rightmost bit positions of the
operand are ignored and are not
preserved in the clock comparator. Special Conditions The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized.
The operation is suppressed on all
addressing and protection exceptions.
Chapter 10. Control Instructions 10-39
Condition Code: The
unchanged.
Program Exceptions:
code
Access (fetch, operand 2)
remains
Operation (if the CPu-timer and clock-comparator facility is
not installed)
Privileged operation
Specification
SET cpu TIMER
SPT [S] '8208' o 16 20 31
The current value of the CPU is
replaced by the contents of the double­
word designated by the second-operand
address.
Only those bits of the operand are set
in the CPU timer that correspond to the
bit positions to be updated; the
contents of the remaining rightmost bit
positions of the operand are ignored and
are not preserved in the CPU timer.
Special Conditions The operand must be designated on a
doubleword boundary; otherwise, a spec­
ification exception is recognized.
The operation is suppressed on all
addressing and protection exceptions. Condition Code: unchanged.
Program Exceptions:
The code
Access (fetch, operand 2)
remains
Operation (if the CPU-timer and
clock-comparator facility is
not installed)
Privileged operation
Specification
SET PREFIX
SPX [S] '8210' o 16 20 31
The contents of the prefix register are
replaced by the contents of bit posi- 10-40 System/370 Principles of Operation
tions 8-19 of the word at the location
designated by the second-operand
address. The translation-lookaside
buffer (TL8) of this CPU is cleared of
entries.
After the second operand is fetched,
depending on the model, the prefix value
mayor may not be tested to determine
whether the corresponding 4K-byte block
in absolute storage is available before
the value is used to replace the
contents of the prefix register.
On models which do not test the value,
the instruction is completed after
setting the prefix register. If the
address loaded designates a location
which is not available in the configura­
tion, then, when an instruction or
interruption procedure is attempted that
requires prefixing to be applied to the
storage address, the CPU suspends opera­
tion. Correction of this condition and
allowing processing to be reinitiated
requires that a reset be performed,
either by means of manual intervention
or by receipt of a SIGNAL PROCESSOR reset order. On models which do test the value, some
or all of the necessary checks are
performed to ensure that the entire
4K-byte block designated by the prefix
address is available. If the storage
area is not available, an addressing
exception is recognized, and the opera­
tion is suppressed. The check to
determine that the 4K-byte block is
available may involve accessing the
location. This access is not subject to
protection; however, the access may
cause the reference bits to be set to
ones.
If the operation is completed, the new
prefix is used for any interruptions
following the execution of the instruc­
tion and for the execution of subsequent
instructions. The contents of bit posi­
tions 0-7 and 20-31 of the operand are ignored.
The translation-lookaside buffer (TLB)
is cleared of entries. The TLB appears
cleared of its original contents, begin­
ning with the fetching of the next
sequential instruction.
A serialization function is performed
before or after the operand is fetched
and again after the operation is
completed.
Special Conditions
The operand must be designated on a word
boundary; otherwise, a specification
exception is recognized.
Previous Page Next Page