Instruction-Processing Damage
Bit 1(PO), when one, indicates that
damage has occurred to the instruction
processing of the cpu.
The exact meaning of bit 1 depends on
the setting of the backed-up bit, bit
14. When the backed-up bit is one, the
condition is called processing backup.
When the backed-up bit is zero, the
condition is called processing damage.
These two conditions are described in
the section "Synchronous Machine-Check
Interruption Conditions" in this
chapter.
Instruction-processing damage can be a
nullifying or a terminating exigent
condition and has no subclass-mask bit.
System RecovervBit 2 (SR), when one, indicates that
malfunctions were detected but did not
result in damage or have been success
fully corrected. Some malfunctions
detected as part of anI/O operation may
result in a system-recovery condition in
addition to an I/O-error condition. The
presence and extent of the system
recovery capability depend on the model.
System recovery is a repressible condition. It is masked by the recovery
subclass-mask bit, which isin bit posi tion 4 of control register 14. Programming Notes
1. System recovery may be used to
report a failing-storage address
detected by aCPU prefetch or by an I/O operation.
2. Unless the corresponding validity
bits are ones, the indication of
system recovery does not imply
storage logical validity, or that
thefields stored as a result of
the machine-check interruption are
valid.
Interval-Timer Damage
Bit 3 (TO), when one, indicates that
damage has occurred to the interval
timer or to the word at real storage
locations80-83. Interval-timer damage is a repressible
condition. It1S masked by the
external-damage subclass-mask bit, which
is in bit position 6 of control register
14.
Timing-Facility Damage
Bit 4(CD), when one, indicates that
damage has occurred to theTOO clock,
theCPU timer, the clock comparator, or
to theCPU-timer or clock-comparator
external-interruption conditions. The
timing-facility-damage machine-check
condition is set whenever any of the
following occurs:
1. TheTOO clock accessed by this CPU enters the error or not-operational
state.
2. TheCPU timer is damaged, and the CPU is enabled for CPU-timer external interruptions. On some
models, this condition may be
recognized even when theCPU is not
enabled forCPU-timer interrup
tions. Depending on the model, the
machine-checkcondition may be
generated only as theCPU timer enters an error state. Or, the
machine-check condition may be
continuously generated whenever theCPU is enabled for CPU-timer inter
ruptions, until theCPU timer is
validated.
3. The clock comparator is damaged,
and theCPU is enabled for clock
comparator external interruptions.On some models, this condition may
be recognized even when theCPU is
not enabled for clock-comparator
interruptions.
Timing-facility damage may also be set
along with instruction-processing damage
when an instruction which accesses theTOO clock, CPU timer, or clock compara
tor produces incorrect results. Depend
ing on the model, theCPU timer or clock
comparator may be validated by the
interruption which reports theCPU timer
or clock comparator as invalid.
Timing-facility damage is a repressible
condition. It is masked by thetiming facility subclass-mask bit, which is in bit position 6 of control register 14. Programming Note
Timing-facility-damage conditions for
theCPU timer and the clock comparator
are not recognized on most models when
these facilities are not in use. Thefacilities are considered not in use
when theCPU is disabled for the corre
sponding external interruptions(PSW bit
7, or the subclass-maskbits, bits 20 and 21 of control register 0, are Chapter 11. Machine-Check Handling 11-17
Bit 1
damage has occurred to the instruction
processing of the cpu.
The exact meaning of bit 1 depends on
the setting of the backed-up bit, bit
14. When the backed-up bit is one, the
condition is called processing backup.
When the backed-up bit is zero, the
condition is called processing damage.
These two conditions are described in
the section "Synchronous Machine-Check
Interruption Conditions" in this
chapter.
Instruction-processing damage can be a
nullifying or a terminating exigent
condition and has no subclass-mask bit.
System Recoverv
malfunctions were detected but did not
result in damage or have been success
fully corrected. Some malfunctions
detected as part of an
result in a system-recovery condition in
addition to an I/O-error condition. The
presence and extent of the system
recovery capability depend on the model.
System recovery is a repressible condi
subclass-mask bit, which is
1. System recovery may be used to
report a failing-storage address
detected by a
2. Unless the corresponding validity
bits are ones, the indication of
system recovery does not imply
storage logical validity, or that
the
the machine-check interruption are
valid.
Interval-Timer Damage
Bit 3 (TO), when one, indicates that
damage has occurred to the interval
timer or to the word at real storage
locations
condition. It
external-damage subclass-mask bit, which
is in bit position 6 of control register
14.
Timing-Facility Damage
Bit 4
damage has occurred to the
the
to the
external-interruption conditions. The
timing-facility-damage machine-check
condition is set whenever any of the
following occurs:
1. The
state.
2. The
models, this condition may be
recognized even when the
enabled for
tions. Depending on the model, the
machine-check
generated only as the
machine-check condition may be
continuously generated whenever the
ruptions, until the
validated.
3. The clock comparator is damaged,
and the
comparator external interruptions.
be recognized even when the
not enabled for clock-comparator
interruptions.
Timing-facility damage may also be set
along with instruction-processing damage
when an instruction which accesses the
tor produces incorrect results. Depend
ing on the model, the
comparator may be validated by the
interruption which reports the
or clock comparator as invalid.
Timing-facility damage is a repressible
condition. It is masked by the
Timing-facility-damage conditions for
the
are not recognized on most models when
these facilities are not in use. The
when the
sponding external interruptions
7, or the subclass-mask