Vector-Facility Source
Bit 13 (VS) ofthe machine-check
interruption code, when one, indicates
that the vector facility is the source
of the reported machine-check condition.
Vector-facility source is reported
together with instruction-processing
damage. When this bit is one, the
contents of vector-facility registers
may have been damaged.
This bit maybe set to one regardless of
whether the vector-control bit, bit 14
of control register0, is one or zero.
Bit 13 is not meaningful when vector
facility failure is reported.
Backed!!.e Bit 14 (B), when one, indicates that the
point of interruption is at a checkpoint
before the point of error. This bit is
meaningful only when the instruction
processing-damage bit, bit 1, is also
set to one. The presence and extent of
the capability to indicate a backed-up
condition depend on the model.
Delayed
Bit 15 (D), when one, indicates that
some or all of the machine-check condi
tions were delayedin being reported
because theCPU was disabled for that
type of interruption at the time the
condition occurred. The bit mayor may
not apply to floating machine-check
interruptions. The presence and extent
of the capability to indicate a delayed
condition depend on the model.
Delayed Access Exception
Bit 34 (DA), whenone, indicates that an
access exception was detected during a
storage access usingOAT when no such
exception was detected by an earlier
test for access exceptions.
Bit 34 is a modifier to instruction
processing damage (bit 1) and is mean
ingful only when bit 1 of the machine
check-interruption code is one. When
bit 1 is zero, bit 34 has no meaning.
The presence and extent of reporting
delayed access exception depend on the
model.
ProgrammingNote The occurrence of a delayed access
exception normally indicates that the
program is uSlng an improper procedure
to update theOAT tables. SYNCHRONOUS MACHINE-CHECK-INTERRUPTION CONDITIONS The instruction-processing damage and
backed-up bits, bits 1 and 14 of the
machine-cheek-interruption code,identi fy, in combination, two conditions.
Bit 1 Bit1i Name of Condition
1
1
o
1Processing damage Processing backup
Processing Backup
The processing-backup condition indi
cates that the point of interruptionis prior to the point, or points, of error.
This is a nullifying exigent condition.
When all of the other CPU-related-damage
subclasses and modifiers of the
machine-cheek-interruption code are zero
and all of the validity bits associated
withCPU status are indicated as valid,
the machine has successfully returned to
a checkpoint prior to the malfunction,
and no damage has yet occurred to the
CPU.
The subclass bits which must be zero for
this to be the case are as follows:
MCIC Bit
o
3
4
6
Name
System damage
Interval-timer damage
Timing-facility damage
Vector-facility failure
The subclass-modifier bits which must be
zero for this to be the case are as
follows:
MCIC Bit
13
34
Vector-facility source
Delayed-access exception
The validity bits in the machine-check
interruption code which mustbe one for
this to be the case are as follows:
Chapter 11. Machine-Check Handling 11-19
Bit 13 (VS) of
interruption code, when one, indicates
that the vector facility is the source
of the reported machine-check condition.
Vector-facility source is reported
together with instruction-processing
damage. When this bit is one, the
contents of vector-facility registers
may have been damaged.
This bit may
whether the vector-control bit, bit 14
of control register
Bit 13 is not meaningful when vector
facility failure is reported.
Backed
point of interruption is at a checkpoint
before the point of error. This bit is
meaningful only when the instruction
processing-damage bit, bit 1, is also
set to one. The presence and extent of
the capability to indicate a backed-up
condition depend on the model.
Delayed
Bit 15 (D), when one, indicates that
some or all of the machine-check condi
tions were delayed
because the
type of interruption at the time the
condition occurred. The bit mayor may
not apply to floating machine-check
interruptions. The presence and extent
of the capability to indicate a delayed
condition depend on the model.
Delayed Access Exception
Bit 34 (DA), when
access exception was detected during a
storage access using
exception was detected by an earlier
test for access exceptions.
Bit 34 is a modifier to instruction
processing damage (bit 1) and is mean
ingful only when bit 1 of the machine
check-interruption code is one. When
bit 1 is zero, bit 34 has no meaning.
The presence and extent of reporting
delayed access exception depend on the
model.
Programming
exception normally indicates that the
program is uSlng an improper procedure
to update the
backed-up bits, bits 1 and 14 of the
machine-cheek-interruption code,
Bit 1 Bit
1
1
o
1
Processing Backup
The processing-backup condition indi
cates that the point of interruption
This is a nullifying exigent condition.
When all of the other CPU-related-damage
subclasses and modifiers of the
machine-cheek-interruption code are zero
and all of the validity bits associated
with
the machine has successfully returned to
a checkpoint prior to the malfunction,
and no damage has yet occurred to the
CPU.
The subclass bits which must be zero for
this to be the case are as follows:
MCIC Bit
o
3
4
6
Name
System damage
Interval-timer damage
Timing-facility damage
Vector-facility failure
The subclass-modifier bits which must be
zero for this to be the case are as
follows:
MCIC Bit
13
34
Vector-facility source
Delayed-access exception
The validity bits in the machine-check
interruption code which must
this to be the case are as follows:
Chapter 11. Machine-Check Handling 11-19