Storage-Key Error Uncorrected
Bit 18 (KE), when one, indicates that a
storage key contained invalid CBC and
that the information could not be
corrected. The contents of the checking
block in the storage key have not been
changed. The storage key may have been
accessed or prefetched for this CPU or
for another CPU or for a or it
may have been accessed as the result of
a model-dependent storage access.
Storage Degradation
Bit 19 (OS), when indicates that
performance degradation has occurred for
the reported storage-error-corrected
condition.
Storage degradation indicates that
although the associated storage error
has been corrected, the correction proc­
ess involved a substantial amount of
time. Thus, this bit indicates that use
of the associated block of storage
should be avoided, if possible.
The indication of storage degradation
has meaning only when bit 17, storage
error corrected, is also one. The pres­ ence and extent of reporting storage
degradation depend on the model.
Programming Note
Because storage degradation is reported
with storage error corrected and, furthermore, because storage error
corrected is normally reported with
system recovery, the recovery subclass
mask, bit 4 of control register 14, should be set to one in order for stor­
age degradation to be indicated.
Indirect Storage Error
Bit 32 (IE), when one, indicates that
the physical main-storage location iden­
tified by the failing-storage address is
not the original source of the error.
Instead, the error originated in another
level of the storage hierarchy and has
been propagated to the current
physical-storage portion of the storage
hierarchy. Bit 32 is meaningful only
when bit 16 or 18 (storage error uncor­
rected or storage-key error uncorrected)
of the machine-check-interruption code
is one. When bits 16 and 18 are both
zeros, bit 32 has no meaning.
For errors originating outside the stor­
age hierarchy, the attempt to store is
rejected, and the appropriate error
indication is presented. When an error
is detected during implicit movement of
information inside the storage
hierarchy, the action is not rejected
and reported in this manner because the
movement may be asynchronous and may be
initiated as the result of an attempt to
access completely unrelated information.
Instead, errors in the contents of the
source during implicit moving of infor­
mation from one portion of the storage
hierarchy to another may be preserved in
the target area by placing a special
invalid CBC in the checking block asso­
ciated with the target location. These
propagated errors, when detected are reported as indirect storage errors.
The original source of such an error may
have been in a cache associated with an I/O processor or a CPU, or the error may
have been the result of a data-path
failure in transmitting data from one
portion of the storage hierarchy to
another. Additionally, a propagated
error may be generated during the move­
ment of data from one physical portion
of storage to another as the result of a
storage-reconfiguration action.
The presence and extent of reporting
indirect storage error depend on the
model.
Programming Note
See the programming notes under TEST BLOCK in Chapter 10, "Control Instructions," for the action which
should be taken after storage errors are reported. MACHINE-CHECK INTERRUPTION-CODE VALIDITY BITS
Bits 20-31, 46, and 47 of the machine­
check-interruption code are validity
bits. Each bit indicates the validity
of a particular field in storage. A
validity bit is meaningless if the asso­
ciated facility is not installed. With
the exception of the storage-logical­
validity bit (bit 31), each bit is
associated with a field stored during
the machine-check interruption. When a
validity bit is one, it indicates that
the saved value placed in the corre­
sponding storage field is valid with
respect to the indicated point of inter­
ruption and that no error was detected
when the data was stored.
When a validity bit is zero, one or more
of the following conditions may have
occurred: the original information was
incorrect, the original information had
invalid CBC, additional malfunctions
were detected while storing the informa- Chapter 11. Machine-Check Handling 11-21

tion, or none or only part of the
information was stored. Even though the
information is unpredictable, the
machine attempts, when possible, to
place valid CBC in the storage field and
thus reduce the possibility of addi­
tional machine checks being caused.
The validity bits for the floating-point
registers, general registers, control
registers, CPU timer, and clock compara­
tor indicate the validity of the saved
value placed in the corresponding save
area. The information in these regis­
ters after the machine-check interrup­
tion is not necessarily correct even
when the correct value has been placed
in the save area and the validity bit
set to one. The use of the registers
and the operation of the facility asso­
ciated with the control registers, CPU timer, and clock comparator, are unpre­
dictable until these registers are
validated. (See the section "Invalid
CBC in Registers" earlier in this chap­
ter.) PSW-EMWP Validity Bit 20 (WP), when one, indicates that
the EMWP bits (bits 12-15) of the
machine-check old PSW are correct. PSW Mask and Key Validity
Bit 21 (MS), when one, indicates that
the system mask, PSW key, and miscella­
neous bits of the machine-check old PSW are correct. Specifically, this bit
covers bits 0-11 of both the EC-mode and
the BC-mode PSWs, and also bits 16, 17,
and 24-39 of the EC-mode PSW. PSW Program-Mask and Condition-Code
Validity
Bit 22 (PM), when one, indicates that
the program mask and condition code of
the machine-check old PSW are correct.
PSW-Instruction-Address Validity
Bit 23 (IA), when one, indicates that
the instruction address (bits 40-63) of
the machine-check old PSW is correct.
11-22 System/370 Principles of Operation Programming Note
When a machine check occurs which stores
aBC-mode PSW, the contents of the
interruption code and ILC in the
machine-check old PSW are unpredictable,
and no PSW-validity bit covers these
bits. The four PSW-validity bits cover
all 64 bits of the EC-mode PSW. Failing-storage-Address Validity
Bit 24 (FA), when one, indicates that a
correct failing-storage address has been
placed at real location 248 after a
storage-error-uncorrected, storage-key­
error-uncorrected, or storage-error­
corrected condition has occurred. The
presence and extent of the capability to
identify the failing-storage location
depend on the model. When no such
errors are reported, that is, bits 16-18
of the machine-check-interruption code
are zeros, the failing-storage address
is meaningless, even though it may be
indicated as valid.
Region-Code Validity
Bit 25 (RC), when one, indicates that a
correct region code has been stored in
the word at real location 252. The
presence of the region code depends on
the model. When a model does not
provide a region code, bit 25 is set to
zero.
External-Damage-Code Validity
Bit 26 (EC), when one, and provided that
bit 5, external damage, is also one,
indicates that a valid external-damage
code has been stored in the word at real
location 244. When bit 5 is zero, bit
26 has no meaning.
Floating-Point-Register Validity
Bit 27 (FP), when one, indicates that
the contents of the floating-point­
register save area at real locations
352-383 reflect the correct state of the
floating-point registers at the point of
interruption. When the floating-point
facility is not installed, this bit is set to zero.