CR4 ASH Second Table
ASH-Second-Table Entry
I ATO STD LTL
(x4)
Authority Table
R
p S
For primary ASH authorization (PT-ss only): Primary-authority exception if P bit
zero or table length exceeded.
For secondary ASH authorization (SSAR-ss only):
Secondary-authority exception if S bit zero or table length exceeded.
For secondary ASH authorization (LASP only):
Set condition code 2 if S bit zero or
table length exceeded.
R: Address is real ASH Authorization
Authority-Table Lookup
The authorization index, in conjunction
with the authority-table orlg1n
contained in the ASH-second-table entry, is used to select an entry from the
authority table.
The authorization index
bit positions 0-15 of
4.
is contained in
control register
Bit positions 8-31 of the AST entry
contain the 24-bit real address of the
authority table (ATO), and bit positions
48-59 contain the length of the authori­
ty table (ATL). The 24-bit real address of a byte in the '1 authority table is obtained by appending I two zeros on the right to the
authority-table orlgln and adding the 14
leftmost bits of the authorization index
with 10 zeros appended on the left. A
carry, if any, into bit position 7 is ignored. With extended real addressing,
this 24-bit real address is extended on
the left with zeros; thus, the authority
table can wrap from 224 - 1 to zero.
As part of the authority-table-entry­
lookup process, bits 0-11 of the author­ ization index are compared against the
authority-table length. If the compared
portion is greater than the authority­
table length, a primary-authority
exception or secondary-authority excep­
tion is recognized for PT-ss or SSAR-ss, respectively. For LOAD ADDRESS SPACE PARAMETERS, when the authority-table
length is exceeded, condition code 2 is
set.
Chapter 3. Storage 3-19

The fetch access to the byte in the
authority table is not subject to
protection. When the storage address
which is generated for fetching the byte
designates a location which is not
available in the configuration, an
addressing exception is recognized, and
the operation is suppressed.
The byte contains four authority-table
entries of two bits each. The rightmost
two bits of the authorization index, bits 14 and 15 of control register 4, are used to select one of the four
entries. The left or right bit of the
entry is then tested, depending on
whether the authorization test is for a
primary ASN or a secondary ASN. The
following table shows the bit which is
selected from the byte as a function of
bits 14 and 15 of the authorization index and the instruction PT-ss, SSAR-ss, or LOAD ADDRESS SPACE PARAME­ TERS. Bit Selected from
Authority-Table Byte
for Test
Authorization-
Index Bits S Bit P Bit (SSAR-ss 14 15 (PT-ss) or LASP) 0 0 0 1 0 1 2 3
1 0 4 5
1 1 6 7
If the selected bit is one, the ASH is
authorized, and the appropriate
address-space-control from
the AST entry are loaded into the appro­
priate control registers. If the
selected bit is zero, the ASH is not
authorized, and a primary-authority
exception or secondary-authority excep­
tion is recognized for PT-ss or SSAR-ss, respectively. For LOAD ADDRESS SPACE PARAMETERS, when the ASH is not author­
ized, condition code 2 is Recognition of Exceptions during ASN Authorization
The exceptions which can be encountered
during the primary-and secondary-ASN­ authorization precesses and their prior­
ities are described in the definitions
of the instructions in which ASH author­ ization is performed. 3-20 System/370 Principles of Operation Programming Note
The primary-and secondary-authority
exceptions cause nullification in order
to permit dynamic modification of the
authority table. Thus, when an address
space is created or "swapped in," the
authority table can first be set to all
zeros and the appropriate authority bits
set to one only when required.
DYNAMIC ADDRESS TRANSLATION Dynamic address translation (OAT)
provides the ability to interrupt the
execution of a program at an arbitrary moment, record it and its data in auxil­ iary storage, such as a direct-access
storage device, and at a later time return the program and the data to
different main-storage locations for
resumption of execution. The transfer
of the program and its data between main
and auxiliary storage may be performed
piecemeal, and the return of the infor­
mation to main storage may take place in response to an attempt by the CPU to
access it at the time it is needed for
execution. These functions may be performed without change or inspection
of the program and its data, do not
require any explicit programming conven­
tion for the relocated program, and do
not disturb the execution of the program
except for the time delay involved.
With appropriate support by an operating
system, the dynamic-address-translation
facility may be used to provide to a
user a system wherein storage appears to
be larger than the main storage which is
available in the configuration. This
apparent main storage is referred to as
virtual storage, and the addresses used
to designate locations in the virtual
storage are referred to as virtual
addresses. The virtual storage of a
user may far exceed the size of the main
storage which is available in the
configuration and normally is maintained
in auxiliary storage. The virtual stor­
age is considered to be composed of
blocks of addresses, called pages. Only the most recently referred-to pages of the virtual storage are assigned to
occupy blocks of physical main storage.
As the user refers to pages of virtual
storage that do not appear in main stor­
age, they are brought in to replace
pages in main storage that are less
likely to be needed. The swapping of
pages of storage may be performed by the
operating system without the user's
knowledge.
The sequence of virtual addresses asso­
ciated with a virtual storage is called
an address space. With appropriate support by an operating system, the
dynamic-address-translation facility may